公开(公告)号：EP2102907A4

公开(公告)日：2013-12-04

申请号：EP07855216

申请日：2007-12-18

Applicant: IBM

Inventor： FRIED DAVID MICHAEL ,  HERGENROTHER JOHN MICHAEL ,  MCNAB SHAREE JANE ,  ROOKS MICHAEL J ,  TOPOL ANNA

IPC: H01L23/544 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/20 ,  G03F9/00 ,  H01J37/317 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84

CPC classification number: G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2008072107A

公开(公告)日：2008-03-27

申请号：JP2007223096

申请日：2007-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHEN GUY ,  CHU JACK OON ,  OTT JOHN ALBRECHT ,  ROOKS MICHAEL J ,  SOLOMON PAUL

IPC: H01L29/786 ,  H01L29/06

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field effect transistor (FET) with a channel formed by a semiconductor nanowire (semiconductor nanowire channel) and doped semiconductor source and drain regions. SOLUTION: A FET structure with a semiconductor nanowire forming the FET channel and doped source and drain regions formed by radial epitaxy from the semiconductor nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有由半导体纳米线（半导体纳米线通道）和掺杂的半导体源极和漏极区域形成的沟道的场效应晶体管（FET）。 解决方案：公开了一种具有形成FET沟道的半导体纳米线和由半导体纳米线体径向外延形成的掺杂源极和漏极区的FET结构。 讨论了顶盖门控和底部门控纳米线FET结构。 源极和漏极制造可以使用选择性或非选择性外延。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2008082942A3

公开(公告)日：2008-09-25

申请号：PCT/US2007087835

申请日：2007-12-18

Applicant: IBM ,  FRIED DAVID MICHAEL ,  HERGENROTHER JOHN MICHAEL ,  MCNAB SHAREE JANE ,  ROOKS MICHAEL J ,  TOPOL ANNA

Inventor： FRIED DAVID MICHAEL ,  HERGENROTHER JOHN MICHAEL ,  MCNAB SHAREE JANE ,  ROOKS MICHAEL J ,  TOPOL ANNA

IPC: H01L23/544

CPC classification number: G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Abstract translation: 一种用于将集成电路芯片的制造水平的第一组特征与包括形成在衬底中的高原子量层的电子束对准目标对准并且使用电子束光刻形成第一组特征并且用于对准第二组特征 将集成电路芯片的相同制造水平的一组特征集合到在衬底中形成的光学对准目标并使用光刻形成第二组特征，光学对准目标本身与电子束对准目标对准。 还有一种形成电子束对准目标的结构的方法。

公开(公告)号：GB2491778A

公开(公告)日：2012-12-12

申请号：GB201217774

申请日：2011-03-23

Applicant: IBM

Inventor： COHEN GUY ,  MURRAY CONAL E ,  ROOKS MICHAEL J

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

公开(公告)号：GB2491778B

公开(公告)日：2014-03-12

申请号：GB201217774

申请日：2011-03-23

Applicant: IBM

Inventor： COHEN GUY ,  MURRAY CONAL E ,  ROOKS MICHAEL J

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

公开(公告)号：DE112011100326T5

公开(公告)日：2012-10-31

申请号：DE112011100326

申请日：2011-03-23

Applicant: IBM

Inventor： COHEN GUY ,  MURRAY CONAL E ,  ROOKS MICHAEL J

IPC: H01L29/775

Abstract: Es werden Techniken zur Einbettung von Silicium-Germanium(e-SiGe)-Source- und Drain-Stressoren in nanoskaligen kanalbasierten Feldeffekttransistoren (FETs) bereitgestellt. Nach einem Aspekt der Erfindung beinhaltet ein Verfahren zum Herstellen eines FET die folgenden Schritte. Ein dotiertes Substrat mit einem darauf befindlichen Dielektrikum wird bereitgestellt. Mindestens ein Silicium-(Si-)Nanodraht wird auf dem Dielektrikum platziert. Ein oder mehrere Teile des Nanodrahtes werden mit einer Maske abgedeckt, wobei andere Teile des Nanodrahtes freiliegend bleiben. Epitaktisches Germanium (Ge) wird auf den freiliegenden Teilen des Nanodrahtes aufgewachsen. Das epitaktische Germanium wird in das Si im Nanodraht eindiffundiert, um die im Nanodraht eingebetteten SiGe-Zonen auszubilden, die die Druckspannung in den Nanodraht einbringen. Das dotierte Substrat dient als Gate des FET, die durch Maske abgedeckten Teile des Nanodrahtes dienen als Kanäle des FET, und die eingebetteten SiGe-Zonen dienen als Source- und Drain-Zonen des FET.