公开(公告)号：CA2245037A1

公开(公告)日：1999-03-18

申请号：CA2245037

申请日：1998-08-14

Applicant: IBM

Inventor： KAHLE JAMES A ,  TRAN CANG N

IPC: G06F13/364 ,  G06F13/40 ,  G06F15/17

Abstract: A method and system for enhanced bus arbitration in a multiprocessor system havi ng multiprocessors coupled to a system memory via a common wide bus. The common wid e bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple pro cessors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a arbitration logic for a number of sub-b uses. A maximum number of sub-buses is specified for each processor and the processors a re prioritized. Each time a bus request is received from a processor, the number of requested sub-buses is granted, if that number is equal to or less than the specified maxi mum number of sub-buses for that processor. If the requested number of sub-buses is greater than the specified maximum number of sub-buses for that processor the requested number is granted if no other processor has issued a bus request.

公开(公告)号：CA2245106C

公开(公告)日：2002-08-06

申请号：CA2245106

申请日：1998-08-14

Applicant: IBM

Inventor： TRAN CANG N ,  KAHLE JAMES A

IPC: G06F13/40 ,  G06F15/17 ,  G06F15/167

Abstract: A method and system for input/output control in a multiprocessor system havi ng multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously in response to one or more transfer requests. In response to a transfer request having a data address associated therewith, a particular target devi ce is identified. The data address is then written into an address queue. Thereafter, one or m ore of the multiple sub-buses are utilized to transfer data to or from a single process or in response to a transfer request from a single processor. In response to a transfer req uest from multiple processors, one or more of the multiple sub-buses may be utilized s eparately to simultaneously transfer data to or from multiple processors.

公开(公告)号：CA2245106A1

公开(公告)日：1999-03-18

申请号：CA2245106

申请日：1998-08-14

Applicant: IBM

Inventor： TRAN CANG N ,  KAHLE JAMES A

IPC: G06F13/40 ,  G06F15/17 ,  G06F15/167

Abstract: A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wid e bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple pro cessors simultaneously in response to one or more transfer requests. In response to a tr ansfer request having a data address associated therewith, a particular target device i s identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor i n response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separ ately to simultaneously transfer data to or from multiple processors.

公开(公告)号：CA2245633C

公开(公告)日：2002-08-06

申请号：CA2245633

申请日：1998-08-14

Applicant: IBM

Inventor： TRAN CANG N ,  KAHLE JAMES A

IPC: G06F13/364 ,  G06F15/167

Abstract: A method and system for enhanced bus access in a multiprocessor system havin g multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each proces sor outputs a request to bus arbitration logic for a maximum-permitted number of sub-bus es. If the number of sub-buses granted to a particular processor equals the number of p ending transactions at that processor, all pending transactions are performed in pa rallel on separate sub-buses. If the number of sub-buses granted is less than the numb er of pending transactions, pending transactions are performed in a priority order . Finally, if the number of granted sub-buses is greater than the number of pending transactio ns, selected transactions are performed over multiple sub-buses in parallel, greatly enha ncing the speed of those transactions.

公开(公告)号：CA2245633A1

公开(公告)日：1999-03-18

申请号：CA2245633

申请日：1998-08-14

Applicant: IBM

Inventor： KAHLE JAMES A ,  TRAN CANG N

IPC: G06F13/364 ,  G06F15/167

Abstract: A method and system for enhanced bus access in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wid e bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple pro cessors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a maximum-permitted number of sub-buses. If the number of sub-buses granted to a particular processor equals the number of pendi ng transactions at that processor, all pending transactions are performed in parall el on separate sub-buses. If the number of sub-buses granted is less than the number o f pending transactions, pending transactions are performed in a priority order. Fi nally, if the number of granted sub-buses is greater than the number of pending transactions, selected transactions are performed over multiple sub-buses in parallel, greatly enhancin g the speed of those transactions.