公开(公告)号：JPH06209090A

公开(公告)日：1994-07-26

申请号：JP24944591

申请日：1991-09-27

Applicant: IBM

Inventor： SAN HOO DON ,  UEI HAN ,  TAIRA YOICHI

IPC: G11C11/407 ,  G11C11/408 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H03K5/02

Abstract: PURPOSE: To minimize substrate effect in a PMOS transistor and to increase the width of the voltage swing of a word line in a word line driver circuit for DRAMs. CONSTITUTION: A separation trench 66 is provided around the N well of a PMOS transistor 58. A pulse generator circuit 52 is provided to give a certain potential to the transistor 58 so that a word line 60 can be shifted to a negative potential on activation. Also, a negative power supply circuit 54 is provided to give a lower potential to the N well when the pulse generator circuit 52 is started.