公开(公告)号：JPH04229482A

公开(公告)日：1992-08-18

申请号：JP13864091

申请日：1991-05-15

Applicant: IBM

Inventor： SHIYAN HOO DON ,  UEI HOWAN

IPC: G11C11/401 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094

Abstract: PURPOSE: To provide a system making possible the prolonging of the reset/ precharge time of a DRAM. CONSTITUTION: A DRAM memory system having plural memory cells arranged in rows and columns is disclosed. This system includes a row address buffer 18 and a circuit for generating a row address strobe signal RASN. A read circuit makes the row address buffer of the DRAM read row addresses. Delay circuits 50, 54 provide a control signal PRASD whose connection time is prolonged which delays the output from the row address buffer in response to a delayed phase transition in which the row address strobe signal is delayed. A reset/precharge circuit 33 becomes an active state during an inactive row address strobe signal and during the control signal whose connection time is prolonged to reset and precharge circuits and memory cells in the DRAM.

公开(公告)号：JPH04233272A

公开(公告)日：1992-08-21

申请号：JP13541491

申请日：1991-04-17

Applicant: IBM

Inventor： SAN FUU DON ,  UEI HOWAN

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94

Abstract: PURPOSE: To provide a new three-dimensional RAM cell structure. CONSTITUTION: This cell structure has a shallow trench access transistor 15 and a deep trench storage capacitor in a well, formed in a semiconductor substrate 10. A vertical access transistor 15 is manufactured, neighboring on one surface of a deep trench storage capacitor 11. By the double-trench cell arrangement, advantages such as miniaturization, high packing density, lower soft error ratio and higher noise margin of the storage capacitor can be obtained, so that superior performance and an effective sensing plan are realized.