公开(公告)号：JPH05159573A

公开(公告)日：1993-06-25

申请号：JP15058092

申请日：1992-06-10

Applicant: IBM

Inventor： SAN FUU DON ,  RUISU MADEISON TAAMAN

IPC: G11C11/409 ,  G11C11/4091

Abstract: PURPOSE: To reduce the dissipation of electric power by holding the reference bit line of a bit line pair at a bit line previous to voltage charging, during the latching and the following rewriting of a sense amplifier. CONSTITUTION: The clock signal of clock signal lines 24 and 26 at the time of starting a refreshing cycle turns on equalizing devices 18 and 20 to charge the bit line pair 22A and 22B to a voltage previous to charging, VEQ. The voltage levels of clock signal lines 32 and 34 are high and the lines 22A and 22B are connected to a sensing amplifier 40. The voltages of lines 28 and 30 turn all the devices of the amplifier 40 to provide sensing amplifier nodes 42 and 44 with the voltage VEQ. In addition, I/O line devices 46 and 48 are in an off state. Along with the operation of the selected line 28, differential voltage is generated between the nodes 42 and 44. Next, the lines 32 and 34 are lowered to turn off bit line separating devices 10 and 12. This separates the amplifier 40 from the lines 22A and 22B.

公开(公告)号：JPH05198176A

公开(公告)日：1993-08-06

申请号：JP21703692

申请日：1992-08-14

Applicant: IBM

Inventor： SAN FUU DON ,  HIYUN JIYON SHIN ,  UEI WAN

IPC: G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  H01L21/822 ,  H01L27/04

Abstract: PURPOSE: To provide a regulator relaxing an electric field on a thin oxide at a word line driver and a circuit related to it, in a worst case without giving adversely affecting the response time of a memory array. CONSTITUTION: The voltage regulator is provided with a band gap reference regulator 30, a first differential amplifier 34 generating a transition voltage from a reference voltage, a first transistor comparing the power source voltage and a boosting voltage, a second transistor comparing the transition voltage and the reference voltage and a latching comparator 44 equalizing outputs from the first and second transistors, so as to define a control signal for an on-chip generator.

公开(公告)号：JPH0685179A

公开(公告)日：1994-03-25

申请号：JP24528892

申请日：1992-09-14

Applicant: IBM

Inventor： SAN FUU DON ,  ROBAATO RUISU FURANCHI

IPC: G05F1/56 ,  H01L27/08 ,  H01L27/092 ,  H03K19/00

Abstract: PURPOSE: To prevent the generation of damage to a CMOS integrated circuit chip due to an excessive surge or a latchup, which is generated in an internal circuit, and to interrupt and clear the state of the latchup. CONSTITUTION: The value of an on-chip power-supply voltage VDD1 outputted to an internal chip circuit 14 by a circuit 10 is compared with the value of a trigger voltage level. When the on-chip power-supply voltage VDD1 is reduced less than the trigger voltage level, a power transistor 18 of a voltage adjusting circuit becomes unusable, the power supply voltage VDD1 is reduced to zero, and the state of a latchup is dissolved. Moreover, the mean current which is made to pass through the transistor 18 extending over several microseconds is detected. When this current exceeds a preset point, the transistor 18 is turned off, the power-supply voltage VDD1 is decreased to zero, and the state of the latchip results in being dissolved.

公开(公告)号：JPH0629488A

公开(公告)日：1994-02-04

申请号：JP6839692

申请日：1992-03-26

Applicant: IBM

Inventor： GEERII BERA BURONAA ,  SAN FUU DON ,  UEI WAN

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To make holding time of cell to be long to the utmost and minimize leak current by enclosing at least one storage means extending from a reverse conductive area to the upper part of a substrate by the embedded insulation collar located within the reverse conductive area. CONSTITUTION: This cell contains a field effect transistor 12 and a trench capacitor 14, which are formed within a semiconductor substrate 16. The transistor 12 is formed within an n-well 18 and it contains a p type source area 20 which is heavily doped. and a drain area 22. It is located within a part 24 of p type of the substrate 16 having the n-well 18 that is lightly doped A memory cell 10 is isolated from other resembling memory cells formed on the substrate 16 by a backward oxide area 26. Then an embedded oxide collar 36 encloses the upper part of a trench 28. Thus, the oxide collar 36 can prevent the depletion of side wall of the trench 28 and minimize leak current.

公开(公告)号：JPH04233272A

公开(公告)日：1992-08-21

申请号：JP13541491

申请日：1991-04-17

Applicant: IBM

Inventor： SAN FUU DON ,  UEI HOWAN

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94

Abstract: PURPOSE: To provide a new three-dimensional RAM cell structure. CONSTITUTION: This cell structure has a shallow trench access transistor 15 and a deep trench storage capacitor in a well, formed in a semiconductor substrate 10. A vertical access transistor 15 is manufactured, neighboring on one surface of a deep trench storage capacitor 11. By the double-trench cell arrangement, advantages such as miniaturization, high packing density, lower soft error ratio and higher noise margin of the storage capacitor can be obtained, so that superior performance and an effective sensing plan are realized.

公开(公告)号：JPH04233271A

公开(公告)日：1992-08-21

申请号：JP13541191

申请日：1991-04-17

Applicant: IBM

Inventor： SAN FUU DON ,  UEI WAN

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To provide a manufacturing method of a DRAM cell, wherein mutual connection between a cell capacitor and an access transistor are self-aligned in the course of the manufacturing process. CONSTITUTION: A method for manufacturing a DRAM cell 10, containing an FET transistor 22 and a capacitor 28 on a single-crystal substrate 30, consists of the following: a process for forming a trench capacitor 28 on a substrate 30, a process for forming a mesa region, a process for forming a channel to the capacitor, a process for sticking a semiconductor layer on the mesa region and the channel, a process for selectively eliminating the semiconductor layer, and a process for forming a gate structure 38, a source region 20 and a drain region 24.