公开(公告)号：JPH05101687A

公开(公告)日：1993-04-23

申请号：JP6564092

申请日：1992-03-24

Applicant: IBM

Inventor： WAGUDEI UIRIAMU ABADEIIA ,  BADEII ERUUKAA ,  UEIN FUREDERITSUKU ERISU ,  DEYUEIN ERUMAA GARUBI ,  NEEZAN RAFUAERU HIRUTEBEITERU ,  UIRIAMU ROBAATO TONTEI ,  JIYOSEFU SAMIYUERU WATSUTSU

IPC: G11C11/413 ,  G11C11/401 ,  G11C17/00 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01L27/10

Abstract: PURPOSE: To program programmable anti and use by a low current value in a short time by providing plural resistors, a connection switching circuit and a program detection circuit. CONSTITUTION: This programmable memory cell 1 for redundant programming is provided with anti and use element resistors F1 and F2 connected through transistors QL1 -QL4 , QP1 and QP2 to nodes N1 and N2. A detection latch circuit 2 serially connects the resistor F1 in response to plural first control signals and parallelly connects the F1 in response to plural second control signals through the transistors QL1 -QL4 . The detection latch 2 compares a first voltage drop over the resistor F1 and a second voltage drop over the F2 and decides the final states of the F1 and F2. One of the nodes N1 is outputted through an inverter composed of Qb1 and Qb2 . An FOUT becomes Vdd at the time of F1>F2 and becomes GND at the time of F1>F2. By the constitution, the memory cell programmable by the low current value in a short time is obtained.

公开(公告)号：JPH08250583A

公开(公告)日：1996-09-27

申请号：JP32275795

申请日：1995-12-12

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  JIYATSUKU ARAN MANDERUMAN ,  UIRIAMU ROBAATO TONTEI

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To improve a leakage current characteristic that is equal to or less than the threshold of a trench-isolated FET device forming a horizontal ledge on the surface of a substrate adjacent to a trench in a silicon substrate and injecting an impurity vertically into the ledge. SOLUTION: A vertical slot that is terminated on the surface of an oxide 12 is formed in a pile-up structure 14 being provided on a silicon substrate 10 that is covered with the oxide film 12, and spacers 20A and 20B are formed on the sidewall of the slot. Then, a trench 22 with sidewalls 26A and 26B that are essentially self-aligned to the slot and are essentially vertical to a bottom part 24. A width that is nearly equal to an interval between the bottom parts of the spacers 20A and 20B are formed in the substrate 10 by etching. Then, the spacers 20A and 20B are eliminated, horizontal ledges 28A and 28B adjacent to the trench 22 are exposed on the exposed surface of the substrate 10 being covered with the oxide 12, and an impurity is injected vertically into the ledges 28A and 28B. The pile-up structure 14 is set to, for example, a silicon nitride layer.