公开(公告)号：JPH08250583A

公开(公告)日：1996-09-27

申请号：JP32275795

申请日：1995-12-12

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  JIYATSUKU ARAN MANDERUMAN ,  UIRIAMU ROBAATO TONTEI

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To improve a leakage current characteristic that is equal to or less than the threshold of a trench-isolated FET device forming a horizontal ledge on the surface of a substrate adjacent to a trench in a silicon substrate and injecting an impurity vertically into the ledge. SOLUTION: A vertical slot that is terminated on the surface of an oxide 12 is formed in a pile-up structure 14 being provided on a silicon substrate 10 that is covered with the oxide film 12, and spacers 20A and 20B are formed on the sidewall of the slot. Then, a trench 22 with sidewalls 26A and 26B that are essentially self-aligned to the slot and are essentially vertical to a bottom part 24. A width that is nearly equal to an interval between the bottom parts of the spacers 20A and 20B are formed in the substrate 10 by etching. Then, the spacers 20A and 20B are eliminated, horizontal ledges 28A and 28B adjacent to the trench 22 are exposed on the exposed surface of the substrate 10 being covered with the oxide 12, and an impurity is injected vertically into the ledges 28A and 28B. The pile-up structure 14 is set to, for example, a silicon nitride layer.

公开(公告)号：JP2012069964A

公开(公告)日：2012-04-05

申请号：JP2011231718

申请日：2011-10-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ASHIMA B CHAKRABARTY ,  ANTHONY I CHOU ,  TOSHIHARU FURUKAWA ,  STEVEN J HOLMES ,  WESLEY C NATAL

IPC: H01L21/205 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13023 ,  H01L2924/1305 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and method for selective deposition of germanium spacers on nitride.SOLUTION: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide in a chemical oxide removal (COR) process and then exposes the heated nitride surface and a oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

Abstract translation: 要解决的问题：提供用于在氮化物上选择性沉积锗间隔物的结构和方法。 解决方案：在半导体制造工艺中选择性地形成锗结构的方法在化学氧化物去除（COR）工艺中去除天然氧化物，然后将加热的氮化物表面和氧化物表面暴露于加热的含锗气体中以选择性地形成 锗仅在氮化物表面上而不是氧化物表面。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：MY115933A

公开(公告)日：2003-09-30

申请号：MYPI19994296

申请日：1999-10-06

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  DAVID V HORAK ,  STEVEN J HOLMES ,  PAUL A RABIDOUX

IPC: H01L21/336 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

Abstract: THE PRESENT INVENTION OVERCOMES THE LIMITATIONS OF THE PRIOR ART TO ALLOW FOR THE CREATION OF SMALLER COMPONENTS FOR USE IN LOGIC CIRCUITS. THE INVENTION PROVIDES A NEW METHOD OF DEFINING AND FONNING FEATURES ON A SEMICONDUCTOR SUBSTRATE BY USING A LAYER OF MATERIAL (210, 1010), REFERRED TO AS A SHADOW MANDREL LAYER, TO CAST A SHADOW (319, 1119, 1508). A TROUGH (312, 1112, 1506) IS ETCHED IN THE SHADOW MANDREL LAYER. AT LEAST ONE SIDE OF THE TROUGH WILL BE USED TO CAST A SHADOW IN THE BOTTOM (313, 1113) OF THE TROUGH. A CONFORMALLY DEPOSITED PHOTORESIST (314, 1114) USED TO CAPTURE THE IMAGE OF THE SHADOW. THE IMAGE OF THE SHADOW IS USED TO DEFINE AND FORM A FEATURE. THIS ALLOWS FOR THE CREATION OF IMAGES ON THE SURFACE OF A WAFER (202, 1002, 1504) WITHOUT THE DIFFRACTION EFFECTS ENCOUNTERED IN CONVENTIONAL PHOTOLITHOGRAPHY. THIS ALLOWS FOR A REDUCED DEVICE SIZE AND INCREASED CHIP OPERATING SPEED.FIG. 1

公开(公告)号：SG80082A1

公开(公告)日：2001-04-17

申请号：SG1999005207

申请日：1999-10-21

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  STEVEN J HOLMES ,  DAVID V HORAK ,  PAUL A RABIDOUX

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  G03C5/58

Abstract: The present invention overcomes the limitations of the prior art to allow for the creation of smaller components for use in logic circuits. The invention provides a new method of defining and forming features on a semiconductor substrate by using a layer of material, referred to as a shadow mandrel layer, to cast a shadow. A trough is etched in the shadow mandrel layer. At least one side of the trough will be used to cast a shadow in the bottom of the trough. A conformally deposited photoresist is used to capture the image of the shadow. The image of the shadow is used to define and form a feature. This allows for the creation of images on the surface of a wafer without the diffraction effects encountered in conventional photolithography. This allows for a reduced device size and increased chip operating speed.

公开(公告)号：SG100658A1

公开(公告)日：2003-12-26

申请号：SG200101933

申请日：2001-03-26

Applicant: IBM

Inventor： ARNE W BALLANTINE ,  JOHN J ELLIS-MONAGHAN ,  TOSHIHARU FURUKAWA ,  GLENN R MILLER ,  JAMES ALBERT SLINKMAN ,  JEFFERY D GILBERT

IPC: H01L21/22 ,  C21D1/04 ,  H01L21/225 ,  H01L21/26 ,  H01L21/265 ,  H01L21/324 ,  H01L21/326 ,  H01L21/00

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

公开(公告)号：SG90085A1

公开(公告)日：2002-07-23

申请号：SG1999006424

申请日：1999-12-17

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK HAKEY ,  STEVEN HOLMES ,  DAVID HORAK ,  PAUL RABIDOUX

IPC: H01L29/78 ,  H01L21/60 ,  H01L21/768 ,  H01L21/318 ,  H01L21/336

Abstract: A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.

公开(公告)号：SG82025A1

公开(公告)日：2001-07-24

申请号：SG1999005186

申请日：1999-10-18

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  STEVEN J HOLMES ,  DAVID V HORAK ,  PAUL A RABIDOUX

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L29/78

Abstract: The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

公开(公告)号：SG80083A1

公开(公告)日：2001-04-17

申请号：SG1999005326

申请日：1999-10-22

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  STEVEN J HOLMES ,  DAVID V HORAK ,  PAUL A RABIDOUX

IPC: H01L21/027 ,  H01L21/768 ,  H01L21/32

Abstract: The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.

公开(公告)号：MY126811A

公开(公告)日：2006-10-31

申请号：MYPI20011417

申请日：2001-03-27

Applicant: IBM

Inventor： JOHN J ELLIS-MONAGHAN ,  TOSHIHARU FURUKAWA ,  ARNE W BALLANTINE ,  GLENN R MILLER ,  JAMES A SLINKMAN ,  JEFFREY D GILBERT

IPC: H01L21/04 ,  H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L21/326

Abstract: A METHOD FOR FORMING A DESIRED JUNCTION PROFILE IN A SEMICONDUCTOR DEVICE . AT LEAST DOPANT IS INTRODUCED INTO A SEMICONDUCTOR SUBSRATE. THE AT LEAST ONE DOPANT IS DIFFUSED IN THE SEMICONDUCTOR SUBSTRATE THROUGH ANNEALING THE SEMICONDUCTOR SUBSTRATE AND THE AT LEAST ONE DOPANT WHILE SIMULTANEOUSLY EXPOSING THE SEMICONDUCTOR SUBSTRATE TO AN ELECTIC FIELD. (FIG. 5)

公开(公告)号：SG102552A1

公开(公告)日：2004-03-26

申请号：SG1999005103

申请日：1999-10-13

Applicant: IBM

Inventor： ARCHIBALD ALLEN ,  TOSHIHARU FURUKAWA ,  EDWARD F O'NEIL ,  MARK C HAKEY ,  ROGER A VERHELST ,  DAVID V HORAK

IPC: H01L21/336 ,  H01L21/768 ,  H01L27/11

Abstract: The present invention overcomes the difficulties found in the background art by providing a direct low resistive contact between devices on a semiconductor chip without excessive current leakage. Current leakage is prevented in the preferred design by using silicon on insulator (SOI) construction for the chip. By constructing the direct contact over an insulator, such as silicon dioxide, current leakage is minimized. The preferred embodiment uses silicide to connect a polysilicon gate to a doped region of the substrate. An alternative embodiment of the present invention provides for the use of conductive studs to electrically connect devices. An increased density of approximately twenty percent may be realized using the present invention.