公开(公告)号：JPH06244379A

公开(公告)日：1994-09-02

申请号：JP31934993

申请日：1993-12-20

Applicant: IBM

Inventor： UORUTAA HAABEI HENKERUSU ,  UEI WAN

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To give a proper signal level and to obtain high density by actualizing a cell of two transistors(TR) and one capacitor by a three-dimensional capacitor manufacture technology. CONSTITUTION: This two-transistor single-capacitor DRAM cell structure consists of a trench capacitor 12, accessed by two TRs 24 and 26 controlled through a common word line 30. Two electrodes of the trench capacitor 12 are connected to a complementary bit line pair. Further, the trench capacitor 12 consists of an internal electrode 16 of a conductive substrate and an external electrode 18 of a conductive substance. A thin layer 20 of an insulator separates the electrodes 16 and 18, and a thick layer 22 of an insulator insulates the capacitor 12 from a substrate 14 and is adjacent to the capacitor on a memory chip. Consequently, a large packaging density is obtained as well as a detection signal can be increased as compared with a single-transistor/single-capacitor DRAM cell.