MEMORY ELEMENT AND ITS FORMATION
    2.
    发明专利

    公开(公告)号:JPH06244379A

    公开(公告)日:1994-09-02

    申请号:JP31934993

    申请日:1993-12-20

    Applicant: IBM

    Abstract: PURPOSE: To give a proper signal level and to obtain high density by actualizing a cell of two transistors(TR) and one capacitor by a three-dimensional capacitor manufacture technology. CONSTITUTION: This two-transistor single-capacitor DRAM cell structure consists of a trench capacitor 12, accessed by two TRs 24 and 26 controlled through a common word line 30. Two electrodes of the trench capacitor 12 are connected to a complementary bit line pair. Further, the trench capacitor 12 consists of an internal electrode 16 of a conductive substrate and an external electrode 18 of a conductive substance. A thin layer 20 of an insulator separates the electrodes 16 and 18, and a thick layer 22 of an insulator insulates the capacitor 12 from a substrate 14 and is adjacent to the capacitor on a memory chip. Consequently, a large packaging density is obtained as well as a detection signal can be increased as compared with a single-transistor/single-capacitor DRAM cell.

    MANUFACTURE OF MEMORY CELL
    3.
    发明专利

    公开(公告)号:JPH04233271A

    公开(公告)日:1992-08-21

    申请号:JP13541191

    申请日:1991-04-17

    Applicant: IBM

    Inventor: SAN FUU DON UEI WAN

    Abstract: PURPOSE: To provide a manufacturing method of a DRAM cell, wherein mutual connection between a cell capacitor and an access transistor are self-aligned in the course of the manufacturing process. CONSTITUTION: A method for manufacturing a DRAM cell 10, containing an FET transistor 22 and a capacitor 28 on a single-crystal substrate 30, consists of the following: a process for forming a trench capacitor 28 on a substrate 30, a process for forming a mesa region, a process for forming a channel to the capacitor, a process for sticking a semiconductor layer on the mesa region and the channel, a process for selectively eliminating the semiconductor layer, and a process for forming a gate structure 38, a source region 20 and a drain region 24.

    DRAM CELL
    4.
    发明专利

    公开(公告)号:JPH0629488A

    公开(公告)日:1994-02-04

    申请号:JP6839692

    申请日:1992-03-26

    Applicant: IBM

    Abstract: PURPOSE: To make holding time of cell to be long to the utmost and minimize leak current by enclosing at least one storage means extending from a reverse conductive area to the upper part of a substrate by the embedded insulation collar located within the reverse conductive area. CONSTITUTION: This cell contains a field effect transistor 12 and a trench capacitor 14, which are formed within a semiconductor substrate 16. The transistor 12 is formed within an n-well 18 and it contains a p type source area 20 which is heavily doped. and a drain area 22. It is located within a part 24 of p type of the substrate 16 having the n-well 18 that is lightly doped A memory cell 10 is isolated from other resembling memory cells formed on the substrate 16 by a backward oxide area 26. Then an embedded oxide collar 36 encloses the upper part of a trench 28. Thus, the oxide collar 36 can prevent the depletion of side wall of the trench 28 and minimize leak current.

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