公开(公告)号：JP2001091825A

公开(公告)日：2001-04-06

申请号：JP2000220238

申请日：2000-07-21

Applicant: IBM

Inventor： BAKER ROBERT G ,  KETTLER KEVIN ,  SUAREZ GUSTAVO A ,  UPLINGER KENNETH A ,  FREEDENBERG CANDACE J F

IPC: G03B15/00 ,  G02B3/00 ,  G02B6/04 ,  G02B6/06 ,  G02B13/04 ,  G02B13/06 ,  G02B13/16 ,  G03B19/00 ,  G06T1/00 ,  H04N5/225 ,  H04N5/232 ,  H04N5/262 ,  H04N7/14 ,  H04N7/15 ,  H04N7/18

Abstract: PROBLEM TO BE SOLVED: To provide an electronic image forming system of a semispherical visual field including a camera receiving the light of the optical image of the semispherical visual field and producing output data corresponding to the optical image. SOLUTION: An optical assembly forming the image covering the whole of the semispherical visual field corresponding to an optical path leading to an imaging element or a photographic film is included in the camera. The optical assembly is provided with a lens component selectively emphasizing the peripheral contents of the semispherical visual field. An electronic imaging element or a film/digital data conversion system arranged in the camera provides an input image memory or an electronic storage device with a digital output signal. A conversion processor accesses the digital output signal selectively from the input image memory and processes according to a user definition reference. Then, the processed signal is stored in an output image memory. The signal in the output image memory is then displayed according to the user definition reference.

公开(公告)号：CA2021834C

公开(公告)日：1993-12-21

申请号：CA2021834

申请日：1990-07-24

Applicant: IBM

Inventor： CAPPS LOUIS B JR ,  FOSTER JIMMY G ,  PRICE WARREN E ,  RUPE ROBERT W ,  UPLINGER KENNETH A

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/16

Abstract: PERSONAL COMPUTER MEMORY BANK PARITY ERROR INDICATOR A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by said one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.

公开(公告)号：CA2021834A1

公开(公告)日：1991-04-07

申请号：CA2021834

申请日：1990-07-24

Applicant: IBM

Inventor： CAPPS LOUIS B JR ,  FOSTER JIMMY G ,  PRICE WARREN E ,  RUPE ROBERT W ,  UPLINGER KENNETH A

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/16

Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.