公开(公告)号：BR9005193A

公开(公告)日：1991-09-17

申请号：BR9005193

申请日：1990-10-16

Applicant: IBM

Inventor： CAPPA LOUIS N JR ,  FORSTER JIMMY G ,  PRICE WILLIAM E ,  RUPE ROBERT W ,  UPLINGER KENNETH ALLEN

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/16

Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.

公开(公告)号：CA2021834C

公开(公告)日：1993-12-21

申请号：CA2021834

申请日：1990-07-24

Applicant: IBM

Inventor： CAPPS LOUIS B JR ,  FOSTER JIMMY G ,  PRICE WARREN E ,  RUPE ROBERT W ,  UPLINGER KENNETH A

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/16

Abstract: PERSONAL COMPUTER MEMORY BANK PARITY ERROR INDICATOR A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by said one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.

公开(公告)号：CA2021834A1

公开(公告)日：1991-04-07

申请号：CA2021834

申请日：1990-07-24

Applicant: IBM

Inventor： CAPPS LOUIS B JR ,  FOSTER JIMMY G ,  PRICE WARREN E ,  RUPE ROBERT W ,  UPLINGER KENNETH A

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/16

Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.