公开(公告)号：JPS63231560A

公开(公告)日：1988-09-27

申请号：JP31546087

申请日：1987-12-15

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

公开(公告)号：JPH09330151A

公开(公告)日：1997-12-22

申请号：JP6089797

申请日：1997-03-14

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

Abstract: PROBLEM TO BE SOLVED: To greatly shorten time delay that a user experiences until productive work becomes ready on a system when the system is powered on again after being powered off, or reset unless a card is replaced in a slot, added, or removed as to a data processing system which has identification values stored on respective cards and performs initialization after the power source is turned on according to those identification values. SOLUTION: A system board 1 includes sockets or slots 2-0-2-7. Input/output option cards 5-0-5-7 can be inserted into those slots so that they can be replaced. Those cards control a variety of peripheral devices which are integrated on the cards or connected through external connectors. Further, the board 1 includes a bus 17 which links a CPU 8, main memory modules 9, 10, and 11 of a RAM, a DMA controller 12, a timing controller 13, a slot and address composite unit 14, other logic elements 15, a power source 16, and a central arithmetic processor with each other or with additional peripheral equipment.

公开(公告)号：JPH06187283A

公开(公告)日：1994-07-08

申请号：JP5714693

申请日：1993-03-17

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

Abstract: PURPOSE: To provide a data processing system where identification values are stored in respective cards and initialization is taken place after power is supplied, based on the identification values. CONSTITUTION: A system board 1 contains a plurality of sockets or slots 2-0 to 2-7. The input/output option cards 5-0 to 5-7 can be inserted into the slots so that they can be exchanged. The cards control various peripheral equipments accumulated in the cards or connected through external connectors. The board 1 contains a bus 17 for mutually linking CPU 8, the main memory modules 9, 10 and 11 of RAM, a DMA controller 12, a timing controller 13, a slot address composite unit 14, the other logic element 15, a power source 16 and a central arithmetic processing unit or connecting them with additional peripheral units.

公开(公告)号：IT1216768B

公开(公告)日：1990-03-08

申请号：IT1955388

申请日：1988-02-26

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F1/00 ,  G06F13/14 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：CA1335843C

公开(公告)日：1995-06-06

申请号：CA557756

申请日：1988-01-29

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F12/00 ,  G06F13/00

Abstract: A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value. That portion of main memory containing the slot positions is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a nonvolatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the table to the card option registers if the status of all the slots has not not changed since the last power-down, system reset, or channel reset.

公开(公告)号：IT8819553D0

公开(公告)日：1988-02-26

申请号：IT1955388

申请日：1988-02-26

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F1/00 ,  G06F13/14 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.