公开(公告)号：JPS63231560A

公开(公告)日：1988-09-27

申请号：JP31546087

申请日：1987-12-15

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

公开(公告)号：JPH09330151A

公开(公告)日：1997-12-22

申请号：JP6089797

申请日：1997-03-14

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

Abstract: PROBLEM TO BE SOLVED: To greatly shorten time delay that a user experiences until productive work becomes ready on a system when the system is powered on again after being powered off, or reset unless a card is replaced in a slot, added, or removed as to a data processing system which has identification values stored on respective cards and performs initialization after the power source is turned on according to those identification values. SOLUTION: A system board 1 includes sockets or slots 2-0-2-7. Input/output option cards 5-0-5-7 can be inserted into those slots so that they can be replaced. Those cards control a variety of peripheral devices which are integrated on the cards or connected through external connectors. Further, the board 1 includes a bus 17 which links a CPU 8, main memory modules 9, 10, and 11 of a RAM, a DMA controller 12, a timing controller 13, a slot and address composite unit 14, other logic elements 15, a power source 16, and a central arithmetic processor with each other or with additional peripheral equipment.

公开(公告)号：JPH06187283A

公开(公告)日：1994-07-08

申请号：JP5714693

申请日：1993-03-17

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

Abstract: PURPOSE: To provide a data processing system where identification values are stored in respective cards and initialization is taken place after power is supplied, based on the identification values. CONSTITUTION: A system board 1 contains a plurality of sockets or slots 2-0 to 2-7. The input/output option cards 5-0 to 5-7 can be inserted into the slots so that they can be exchanged. The cards control various peripheral equipments accumulated in the cards or connected through external connectors. The board 1 contains a bus 17 for mutually linking CPU 8, the main memory modules 9, 10 and 11 of RAM, a DMA controller 12, a timing controller 13, a slot address composite unit 14, the other logic element 15, a power source 16 and a central arithmetic processing unit or connecting them with additional peripheral units.

公开(公告)号：AU554821B2

公开(公告)日：1986-09-04

申请号：AU1073583

申请日：1983-01-25

Applicant: IBM

Inventor： HEATH CHESTER A

IPC: G06F13/12 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F17/21 ,  G06F3/00 ,  G06F13/00

Abstract: This adapter contains two separately controllable sections, each transferring data in various formats between a peripheral device interface and either a microprocessor contained in an associated I/O controller or a host processor or both. Dedicated controls enable the adapter to operate autonomously after being prepared by the microprocessor. Separate but interconnectable handshaking controls enable the sections to operate either asynchronously or in time coordination with each other. Handshaking controls in plural adapters are interconnectable to coordinate related transfers of data between a device and one or more hosts via plural adapter paths. Programmable commands enable the microprocessor to condition the adapter to conduct various data transfers autonomously. Such data can be transferred to or from the device interface in various bit-parallel formats defined by the commands, and from or to the host processor, the microprocessor, or both the host processor and microprocessor concurrently. In one handshaking mode, the adapter sustains an array indexing operation in which one section transfers "address" data to a device and the other section transfers "addressed" portions of a data array between the same device and either the host processor or the microprocessor.

公开(公告)号：AU552852B2

公开(公告)日：1986-06-26

申请号：AU1094083

申请日：1983-02-02

Applicant: IBM

Inventor： HEATH CHESTER A ,  DUREN RICHARD G VAN

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/12 ,  G06F13/28 ,  G06F15/17 ,  G06F15/177 ,  G06F3/00

Abstract: A dual mode microprocessor acts either as a front-end IO controller processor relative to a primary host processor and device or as a secondary data processor having independent storage, processing and IO capabilities. Host software prepares a list of device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor so as to evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, performing this transfer in an autonomous manner, i.e., without assistance from either processor. In PO mode the microprocessor directs associated elements to perform one or more programs of operations defined by secondary commands contained in a command list which is transferred to the microprocessor's memory by special PO mode "LOAD" type DCB's, and interpreted in response to special PO mode type "START" DCB's. A list transferred by one LOAD DCB may be repeatedly accessed at various positions by several START DCB's. The architecture of the command list includes commands which permit the microprocessor to exchange data with the host and/or a device, perform arithmetic operations on data, perform bit and byte manipulative operations on data, and directly control the device interface.

公开(公告)号：DE2965878D1

公开(公告)日：1983-08-18

申请号：DE2965878

申请日：1979-12-04

Applicant: IBM

Inventor： HEATH CHESTER A

IPC: G06F5/06 ,  G06F5/10 ,  G06F13/00

Abstract: A data buffer system is provided for controlling the transfer of data between a processor and an input/output (I/O) device and includes a data storage device having a maximum data storage capacity value. The data storage device is disposed between the processor and the I/O device for receiving data input from the processor and for outputting data to the I/O device to thereby transfer data from the processor to the I/O device. The data storage device temporarily stores a predetermined amount of data while simultaneously transferring data between the processor and the I/O device. Circuitry is provided for selectively establishing a threshold storage capacity value of the data storage device wherein the threshold storage capacity value is less than the maximum storage capacity value of the data storage device. Circuitry is further provided for maintaining the predetermined amount of data temporarily stored in the data storage device equal to the threshold storage capacity value while the data storage device receives data from the processor and outputs data to the I/O device.

公开(公告)号：MX153125A

公开(公告)日：1986-08-06

申请号：MX19610783

申请日：1983-02-01

Applicant: IBM

Inventor： HEATH CHESTER A

IPC: G06F13/12 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F17/21 ,  G06F13/20

Abstract: This adapter contains two separately controllable sections, each transferring data in various formats between a peripheral device interface and either a microprocessor contained in an associated I/O controller or a host processor or both. Dedicated controls enable the adapter to operate autonomously after being prepared by the microprocessor. Separate but interconnectable handshaking controls enable the sections to operate either asynchronously or in time coordination with each other. Handshaking controls in plural adapters are interconnectable to coordinate related transfers of data between a device and one or more hosts via plural adapter paths. Programmable commands enable the microprocessor to condition the adapter to conduct various data transfers autonomously. Such data can be transferred to or from the device interface in various bit-parallel formats defined by the commands, and from or to the host processor, the microprocessor, or both the host processor and microprocessor concurrently. In one handshaking mode, the adapter sustains an array indexing operation in which one section transfers "address" data to a device and the other section transfers "addressed" portions of a data array between the same device and either the host processor or the microprocessor.

公开(公告)号：AU552910B2

公开(公告)日：1986-06-26

申请号：AU1078483

申请日：1983-01-26

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  HEATH CHESTER A ,  MEAD JUSTIN E ,  DUREN RICHARD G VAN ,  JANES GARY A

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00 ,  G06F13/00

Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.

公开(公告)号：CA1184313A

公开(公告)日：1985-03-19

申请号：CA419287

申请日：1983-01-12

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  HEATH CHESTER A ,  MEAD JUSTIN E ,  VAN DUREN RICHARD G ,  JANES GARY A

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00

Abstract: PERIPHERAL ATTACHMENT INTERFACE FOR I/O CONTROLLER HAVING CYCLE STEAL AND OFF-LINE MODES This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.

公开(公告)号：AU1073583A

公开(公告)日：1983-08-11

申请号：AU1073583

申请日：1983-01-25

Applicant: IBM

Inventor： HEATH CHESTER A

IPC: G06F13/12 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F17/21 ,  G06F3/00 ,  G06F13/00

Abstract: This adapter contains two separately controllable sections, each transferring data in various formats between a peripheral device interface and either a microprocessor contained in an associated I/O controller or a host processor or both. Dedicated controls enable the adapter to operate autonomously after being prepared by the microprocessor. Separate but interconnectable handshaking controls enable the sections to operate either asynchronously or in time coordination with each other. Handshaking controls in plural adapters are interconnectable to coordinate related transfers of data between a device and one or more hosts via plural adapter paths. Programmable commands enable the microprocessor to condition the adapter to conduct various data transfers autonomously. Such data can be transferred to or from the device interface in various bit-parallel formats defined by the commands, and from or to the host processor, the microprocessor, or both the host processor and microprocessor concurrently. In one handshaking mode, the adapter sustains an array indexing operation in which one section transfers "address" data to a device and the other section transfers "addressed" portions of a data array between the same device and either the host processor or the microprocessor.