公开(公告)号：JP2007287141A

公开(公告)日：2007-11-01

申请号：JP2007099182

申请日：2007-04-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RONALD HALL ,  CHRISTOPHER M ABERNATHY ,  KURT ALAN FAIST ,  VAN NORSTRAND ALBERT J JR

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/524

Abstract: PROBLEM TO BE SOLVED: To provide a system and method for placing a processor into a gradual slow-down mode of operation. SOLUTION: The gradual slow-down mode in this system has a plurality of stages of slow-down operation of an issuing unit 330 in a processor 300 in which the issuance of instructions is slowed in accordance with a staging scheme as shown in Figure 4. The gradual slow-down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow-down is gradual, the processor may flexibly avoid various degrees of livelock conditions. A mechanism of an illustrative embodiment influences the overall processor performance based on the severity of the livelock condition by taking a small performance influence on a less severe livelock condition and only increasing influence on the processor performance when the livelock condition is more severe. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于将处理器置于逐渐减速操作模式的系统和方法。 解决方案：该系统中的逐渐减速模式在处理器300中具有发放单元330的多个阶段的减速操作，其中指令的发出根据如下所示的分段方案而变慢 图4.处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 示例性实施例的机制通过对较不严格的活锁状态采取较小的性能影响，并且仅当活锁状态更严重时才对处理器性能的影响增加，基于活锁状态的严重性来影响整体处理器性能。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006351008A

公开(公告)日：2006-12-28

申请号：JP2006156065

申请日：2006-06-05

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER M ,  DEMENT JONATHAN J ,  VAN NORSTRAND ALBERT J JR ,  SHIPPY DAVID

IPC: G06F9/38 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for blocking threads upon dispatch of a multithread processor, computer program, and device for controlling thread performance minutely. SOLUTION: A plurality of threads commonly use a pipeline within a processor. Therefore, a condition of long latency time for an instruction of one thread can stop all threads commonly using the pipeline. A dispatch block signal instruction blocks the thread including the condition of the long latency time upon the dispatch. Since a blocking duration equals the length of the latency time, the pipeline can dispatch an instruction from the blocked thread after the condition of the long latency time is released. The processor can dispatch an instruction from the other threads during blocking by blocking one thread upon dispatch. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：JP2006285990A

公开(公告)日：2006-10-19

申请号：JP2006088892

申请日：2006-03-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DEMENT JONATHAN J ,  FEISTE KURT ALAN ,  RAY DAVID S ,  SHIPPY DAVID ,  VAN NORSTRAND ALBERT J JR

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3867

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for processing multicycle non-pipelined command sequencing. SOLUTION: In the system and the method, when a non-pipelined command is detected at an issuing point, issuing logic begins a stall in the minimum number of cycles, enough to complete the highest-speed non-pipelined command. Subsequently, an execution unit succeeds the stall until the non-pipelined command has actually been completed. Slightly before completing the command, the execution unit releases the stall to the issuing logic. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种处理多循环非流水线命令排序的系统和方法。 解决方案：在系统和方法中，当在发布点检测到非流水线命令时，发出逻辑以最小数量的循环开始停顿，足以完成最高速度的非流水线命令。 随后，执行单元成功停止，直到非流水线命令实际完成。 在完成命令之前，执行单元将释放失速到发行逻辑。 版权所有（C）2007，JPO＆INPIT