中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.02 seconds)

    IMPROVED TLB MANAGEMENT FOR REAL-TIME APPLICATIONS
    1.
    发明申请
    IMPROVED TLB MANAGEMENT FOR REAL-TIME APPLICATIONS 审中-公开
    改进TLB管理实时应用程序

    公开(公告)号：WO2004053698A3

    公开(公告)日：2006-01-12

    申请号：PCT/GB0305108

    申请日：2003-11-21

    Applicant: IBM ,  IBM UK

    Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

    IPC: G06F12/10 ,  G06F12/12

    CPC classification number: G06F12/1027 ,  G06F12/126

    Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

    Abstract translation: 计算机系统中的存储器管理通过防止地址转换信息的一部分被替换为高速缓冲存储器中的其他类型的地址转换信息而被改进，该高速缓冲存储器被保留用于存储用于CPU更快速访问的这种地址转换信息。 这样，CPU可以识别存储在高速缓存中的地址转换信息的子集。

    SYSTEM AND METHOD FOR DYNAMIC POWER MANAGEMENT IN A PROCESSOR DESIGN
    2.
    发明申请
    SYSTEM AND METHOD FOR DYNAMIC POWER MANAGEMENT IN A PROCESSOR DESIGN 审中-公开
    处理器设计中用于动态电源管理的系统和方法

    公开(公告)号：WO2007039412A3

    公开(公告)日：2007-10-04

    申请号：PCT/EP2006066249

    申请日：2006-09-11

    Applicant: IBM ,  IBM UK ,  ABERNATHY CHRISTOPHER MICHAEL ,  DEMENT JONATHAN JAMES ,  HALL RONALD ,  PHILHOWER ROBERT ALAN ,  SHIPPY DAVID

    Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  DEMENT JONATHAN JAMES ,  HALL RONALD ,  PHILHOWER ROBERT ALAN ,  SHIPPY DAVID

    IPC: G06F1/32 ,  G06F9/38

    CPC classification number: G06F1/3237 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3867 ,  Y02D10/128 ,  Y02D10/152

    Abstract: A system and method for dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

    Abstract translation: 介绍了一种用于处理器设计中的动态功率管理的系统和方法。 流水线级的失速检测逻辑检测到失速条件，并向空闲检测逻辑发送信号以关闭流水线的寄存器时钟。 失速检测逻辑还监测下游流水线级的失速状况，并且当下游流水线级也处于失速状态时，指示空闲检测逻辑门控关闭流水线级的寄存器。 另外，当流水线级的失速检测逻辑检测到来自下游流水线级或来自它自己的流水线单元的失速条件时，流水线级的失速检测逻辑通知上游流水线级关闭其时钟，从而节省更多功率 。

    Method and device for issuing instruction from issue queue in information processing system
    3.
    发明专利
    Method and device for issuing instruction from issue queue in information processing system 有权
    在信息处理系统中发现问题的方法和装置

    公开(公告)号：JP2007095061A

    公开(公告)日：2007-04-12

    申请号：JP2006261269

    申请日：2006-09-26

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JONATHAN JAMES DEMENT ,  FEISTE KURT ALAN ,  CHRISTOPHER MICHAEL ABERNATHY ,  SHIPPY DAVID

    IPC: G06F9/38

    CPC classification number: G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3855

    Abstract: PROBLEM TO BE SOLVED: To provide a method for issuing instructions from an issue queue. SOLUTION: A processor includes the issue queue that can advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns which are coupled to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward a first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue, a stall condition occurs for that instruction. However, to prevent the entire issue queue and the processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种从发布队列发出指令的方法。

    解决方案：处理器包括可以提前发布问题的问题队列，即使队列中的某些指令还没有准备就绪。 问题队列包括以行和列配置的存储单元的矩阵，其被耦合到执行单元。 显示从空行到无存储单元格时，逐行发行的说明。 当指令向第一行发送时，并且在发行时出现未占用的单元。 当特定行包含不能准备发出的指令时，该指令将发生停顿状态。 然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。 因此，对执行单元的指令的无序发布继续进行。 版权所有（C）2007，JPO＆INPIT

    Apparatus and method for handling data cache miss out-of-order for asynchronous pipeline
    5.
    发明专利
    Apparatus and method for handling data cache miss out-of-order for asynchronous pipeline 有权
    用于处理数据缓存的装置和方法不适用于异步管道

    公开(公告)号：JP2007207238A

    公开(公告)日：2007-08-16

    申请号：JP2007019199

    申请日：2007-01-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHRISTOPHER MICHAEL ABERNATHY ,  RONALD HALL ,  BRADFORD JEFFREY POWERS ,  SHIPPY DAVID ,  HEIL TIMOTHY HUME

    IPC: G06F9/38 ,  G06F12/08

    CPC classification number: G06F9/30043 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3861

    Abstract: PROBLEM TO BE SOLVED: To provide an apparatus for handling data cache misses out-of-order for a plurality of asynchronous pipelines. SOLUTION: This apparatus associates a load tag (LTAG) identifier with a load instruction, and constantly monitors load instructions across multiple pipelines as indexes to the load table data structure of the load target buffer. The load table manages the cache hits/misses, and is used to aid in the recycling of data from the L2 cache. When the load instruction is issued and the corresponding entry in the load table is seen as what is marked as "miss", the effects of issuance of the load instruction are canceled. The load instruction is stored in the load table for future reissuing to the instruction pipe line when the requested data is recycled. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于处理多个异步管线的无序数据高速缓存未命中的装置。 解决方案：该装置将负载标签（LTAG）标识符与加载指令相关联，并且不断监视跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。 加载表管理缓存命中/未命中，并用于帮助从L2缓存中回收数据。 当发出加载指令并且将负载表中的相应条目视为标记为“未命中”的情况时，将取消发出加载指令的效果。 加载指令存储在加载表中，以便在请求的数据被回收时将来重新发布到指令管道。 版权所有（C）2007，JPO＆INPIT

    METHOD FOR BLOCKING THREAD UPON DISPATCH OF MULTITHREAD PROCESSOR, COMPUTER PROGRAM, AND DEVICE (MINUTE MULTITHREAD DISPATCH LOCK MECHANISM)
    6.
    发明专利
    METHOD FOR BLOCKING THREAD UPON DISPATCH OF MULTITHREAD PROCESSOR, COMPUTER PROGRAM, AND DEVICE (MINUTE MULTITHREAD DISPATCH LOCK MECHANISM) 审中-公开

    公开(公告)号：JP2006351008A

    公开(公告)日：2006-12-28

    申请号：JP2006156065

    申请日：2006-06-05

    Applicant: IBM

    Inventor： ABERNATHY CHRISTOPHER M ,  DEMENT JONATHAN J ,  VAN NORSTRAND ALBERT J JR ,  SHIPPY DAVID

    IPC: G06F9/38 ,  G06F9/46

    Abstract: PROBLEM TO BE SOLVED: To provide a method for blocking threads upon dispatch of a multithread processor, computer program, and device for controlling thread performance minutely. SOLUTION: A plurality of threads commonly use a pipeline within a processor. Therefore, a condition of long latency time for an instruction of one thread can stop all threads commonly using the pipeline. A dispatch block signal instruction blocks the thread including the condition of the long latency time upon the dispatch. Since a blocking duration equals the length of the latency time, the pipeline can dispatch an instruction from the blocked thread after the condition of the long latency time is released. The processor can dispatch an instruction from the other threads during blocking by blocking one thread upon dispatch. COPYRIGHT: (C)2007,JPO&INPIT

    IN ORDER MULTITHREADING RECYCLE AND DISPATCH MECHANISM
    8.
    发明专利
    IN ORDER MULTITHREADING RECYCLE AND DISPATCH MECHANISM 未知

    公开(公告)号：CA2503079A1

    公开(公告)日：2004-06-17

    申请号：CA2503079

    申请日：2003-10-22

    Applicant: IBM

    Inventor： VAN NORSTRAND ALBERT JAMES JR ,  SHIPPY DAVID ,  FEISTE KURT ALAN

    IPC: G06F7/38 ,  G06F9/312 ,  G06F9/345 ,  G06F9/38 ,  G06F15/00

    Abstract: A system and method is provided for improving throughput of an in-order multithreading processor. A dependent instruction is identified to follow at least one long latency instruction with register dependencies from a first thread. The dependent instruction is recycled by providing it to an earlier pipeline stage. The dependent instruction is delayed at dispatch. The completion of the long latency instruction is detected from the first thread . An alternate thread is allowed to issue one or more instructions while the long latency instruction is being executed.

    9.
    发明专利
    未知

    公开(公告)号：AT390667T

    公开(公告)日：2008-04-15

    申请号：AT03812611

    申请日：2003-11-21

    Applicant: IBM

    Inventor： DAY MICHAEL ,  HOFSTEE HARM ,  JOHNS CHARLES ,  KAHLE JAMES ,  TRUONG THUONG ,  SHIPPY DAVID

    IPC: G06F12/10 ,  G06F12/12

    Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

Patent Agency Ranking