公开(公告)号：CA2503079A1

公开(公告)日：2004-06-17

申请号：CA2503079

申请日：2003-10-22

Applicant: IBM

Inventor： VAN NORSTRAND ALBERT JAMES JR ,  SHIPPY DAVID ,  FEISTE KURT ALAN

IPC: G06F7/38 ,  G06F9/312 ,  G06F9/345 ,  G06F9/38 ,  G06F15/00

Abstract: A system and method is provided for improving throughput of an in-order multithreading processor. A dependent instruction is identified to follow at least one long latency instruction with register dependencies from a first thread. The dependent instruction is recycled by providing it to an earlier pipeline stage. The dependent instruction is delayed at dispatch. The completion of the long latency instruction is detected from the first thread . An alternate thread is allowed to issue one or more instructions while the long latency instruction is being executed.