公开(公告)号：DE10110504A1

公开(公告)日：2001-10-18

申请号：DE10110504

申请日：2001-03-03

Applicant: IBM

Inventor： DAVIS GORDON TAYLOR ,  HEDDES MARCO C ,  LEAVENS ROSS BOYD ,  VERPLANKEN FRABRICE JEAN

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16

Abstract: The method involves providing several instruction execution threads as independent processes in a sequential time frame. The execution threads are arranged in a queue so that they have overlapping access to the accessible data. A first thread in the queue is executed, and the execution control is transferred to the next thread in the queue when an event occurs that blocks the execution of the first thread. Independent claims are included for a processing system, a method of executing several independent threads in a processor, the use of a prefetch buffers in connection with a number of independent instruction threads, and for a thread execution controller.

公开(公告)号：DE10110504B4

公开(公告)日：2006-11-23

申请号：DE10110504

申请日：2001-03-03

Applicant: IBM

Inventor： DAVIS GORDON TAYLOR ,  HEDDES MARCO C ,  LEAVENS ROSS BOYD ,  VERPLANKEN FRABRICE JEAN

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16

Abstract: A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.