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    QUEUE MANAGER FOR BUFFER
    7.
    发明专利
    QUEUE MANAGER FOR BUFFER 失效

    公开(公告)号：JP2001222505A

    公开(公告)日：2001-08-17

    申请号：JP2000384352

    申请日：2000-12-18

    Applicant: IBM

    Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO C ,  SIEGEL MICHAEL STEVEN ,  MICHAEL RAYMOND TROMBLAY ,  VERPLANKEN FABRICE JEAN

    IPC: G06F12/00 ,  G06F5/06 ,  G06F5/14 ,  G06F12/02 ,  G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/38

    Abstract: PROBLEM TO BE SOLVED: To provide a bandwidth maintenance queue manager for (first-in first-out)FIFO buffer provided with another DRAM storage device for maintaining a FIFO queue. SOLUTION: A FIFO buffer is used on an ASIC chip so that plural queue entries can be stored and retrieved. As long as the total size of queues does not exceed a usable storage device in the buffer, any data storage device is not required more. When supplied data exceeds the buffer storage space of a certain prescribed quantity in the FIFO buffer, however, these data are written in the other data storage device in the form of packet and read from that storage device. That packet has an optimal size for maintaining the peak performance of the data storage device and is written in the data storage device in a way such as queuing with the address sequence of FIFO.

    PATTERN RANGE COMPARISON IMPLEMENTING METHOD, COMPUTER-READABLE MEDIUM, AND DEVICE
    8.
    发明专利
    PATTERN RANGE COMPARISON IMPLEMENTING METHOD, COMPUTER-READABLE MEDIUM, AND DEVICE 失效

    公开(公告)号：JP2002024293A

    公开(公告)日：2002-01-25

    申请号：JP2001104687

    申请日：2001-04-03

    Applicant: IBM

    Inventor： CALVIGNAC JEAN LOUIS ,  HEDDES MARCO C ,  JEFFERIES CLARK DEBUS ,  PATEL PIYUSH CHUNILAL ,  RINALDI MARK ANTHONY

    IPC: G06F17/30 ,  H04L12/56

    Abstract: PROBLEM TO BE SOLVED: To provide a new data structure, a method, and a device for a software management tree(SMT) which provide a control point processor. SOLUTION: This retrieving mechanism reduces the storage space of a node by using only a forward pointer together with a next bit or bit group to be tested next. Multiple retrieval is unnecessary and filter rules for an application are processed to make it possible to connect various filter rules. Two patterns of the same length are stored in respective leaves to define range comparison. Final comparing operation is comparison within a range or comparison below a mask. Through the comparison within the range, it is decided whether or not an input key is within the range defined by the two patterns. Through the comparison below the mask, various bits in the input key are compared with various bits in a 1st leaf pattern under the mask specified with the 2nd leaf pattern.

    MULTI-THREAD USING METHOD, MULTI-THREAD PROCESSING SYSTEM, THREAD EXECUTION CONTROLLER, AND BUFFER USING METHOD
    9.
    发明专利
    MULTI-THREAD USING METHOD, MULTI-THREAD PROCESSING SYSTEM, THREAD EXECUTION CONTROLLER, AND BUFFER USING METHOD 失效

    公开(公告)号：JP2001350638A

    公开(公告)日：2001-12-21

    申请号：JP2001104520

    申请日：2001-04-03

    Applicant: IBM

    Inventor： DAVIS GORDON TAYLOR ,  HEDDES MARCO C ,  LEAVENS ROSS BOYD ,  VERPLANKEN FABRICE JEAN

    IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16

    Abstract: PROBLEM TO BE SOLVED: To attain the more efficient use of a processor resource. SOLUTION: When an execution is permitted in a thread that is stopping the acting, a prefetch buffer 118 is used in relation to a plurality of independent thread processings in a method as avoids an instantaneous stop. In order to realize the more efficient use of the processor resource, a mechanism 30 for controlling the switching from the thread within a processor to another thread is established. This mechanism imparts a temporary control to the alternative execution thread when a short waiting time event is generated, and imparts a perfect control to the alternative execution thread when a long waiting time even is generated. This thread control mechanism comprises a priority FIFO constituted so that the execution priorities of at least two execution threads within the processor are controlled according to their outputs on the basis of the length of the time when each execution thread is stayed within an FIFO 52.

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