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公开(公告)号:EP1226501A4
公开(公告)日:2003-10-01
申请号:EP00959158
申请日:2000-08-24
Applicant: IBM
Inventor: BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , RAO SRIDHAR , SIEGEL MICHAEL STEVEN , YOUNGMAN BRIAN ALAN , VERPLANKEN FABRICE JEAN
IPC: G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56 , G06F13/00 , G06F13/38 , G06F15/00 , G06F15/173 , G06F15/76
CPC classification number: H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
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公开(公告)号:EP1208676A4
公开(公告)日:2008-02-27
申请号:EP00959159
申请日:2000-08-24
Applicant: IBM
Inventor: ALLEN JAMES JR , BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GAUR SANTOSH PRASAD , HEDDES MARCO C , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
CPC classification number: H04Q3/002 , H04L45/742 , H04L49/254 , H04L49/351 , H04L49/354 , H04L49/602 , H04L2212/00 , H04Q3/5455 , H04Q2213/1302 , H04Q2213/13034 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13322
Abstract: A network switching apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors (12) and a suite of peripheral elements formed on a semiconductor substrate (10). The interface processors (12) and peripherals together form a network processor capable of cooperating with other elements including an optional switch fabric device in executing instructions directing the flow of data in the network.
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公开(公告)号:EP1222517A4
公开(公告)日:2007-03-21
申请号:EP00957270
申请日:2000-08-24
Applicant: IBM
Inventor: BARKER KENNETH JAMES , BASS BRIAN MITCHELL , CALVIGNAC JEAN-LOUIS , HEDDES MARCO C , SIEGEL MICHAEL STEVEN , TROMBLEY MICHAEL RAYMOND , VERPLANKEN FABRICE JEAN
CPC classification number: H04L29/06 , H04L49/1507 , H04L49/45 , H04L69/12
Abstract: A network processor (10) useful in network switch apparatus and methods of operating such a processor (10) in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors (16, 34) formed on a semiconductor substrate. The interface processors (16, 34) provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
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公开(公告)号:EP1226509A4
公开(公告)日:2007-09-26
申请号:EP00957269
申请日:2000-08-24
Applicant: IBM
Inventor: BASS BRIAN MITCHELL , CALVIGNAC JEAN-LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , LEAVENS ROSS BOYD , PATEL PIYUSH CHUNILAL , RINALDI MARK ANTHONY , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
CPC classification number: H04L49/602 , G06F15/80 , H04L49/351
Abstract: A network processor (10) useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex (12) with a suite of peripherals (14-36 and 40), all formed on a common semiconductor substrate. The interface processors (16, 34) provide data path for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
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公开(公告)号:EP1208447A4
公开(公告)日:2004-10-20
申请号:EP00959157
申请日:2000-08-24
Applicant: IBM
Inventor: BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO C , PATEL PIYUSH CHUNILAL , REVILLA JUAN GUILLERMO , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
IPC: G06F15/167 , G06F12/06 , G06F15/177 , H04L12/56 , H04Q11/04 , G06F15/16 , G06F12/00 , G06F13/16
CPC classification number: H04Q11/0478 , H04L2012/5681
Abstract: A network switch apparatus (10), components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate (10). The memory elements and interface processors together form a network processor (10) capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by a plurality of processors.
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公开(公告)号:JP2002057688A
公开(公告)日:2002-02-22
申请号:JP2001104637
申请日:2001-04-03
Applicant: IBM
Inventor: GALLO ANTHONY MATTEO , HARIHARAN SEETA , HEDDES MARCO C , SURIDARU RAAO , VERRILLI COLIN BEATON , GAIL EILEEN WOODLAND
IPC: G06F15/167 , G06F9/44 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/14 , H04L12/24 , H04L12/44 , H04L12/46 , H04L12/56 , H04L29/06
Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for managing a memory in a network processing system for providing the allocation of a physical memory section inside a network processor connected to a control point processor by a bus. SOLUTION: This allocation system provides a memory management layer without the need of a complete operating system interface and supports the asynchronous completion of allocation requests. Multicast allocation is supported and the allocation can be simultaneously requested on the plural network processors. An allocation mechanism returns a token, then a memory position is accessed by a protocol through the bus by using the token, and the allocation performed on the plural network processors where actual physical addresses and memory constitution are different is referred to by a single token.
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公开(公告)号:JP2001222505A
公开(公告)日:2001-08-17
申请号:JP2000384352
申请日:2000-12-18
Applicant: IBM
Inventor: BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO C , SIEGEL MICHAEL STEVEN , MICHAEL RAYMOND TROMBLAY , VERPLANKEN FABRICE JEAN
IPC: G06F12/00 , G06F5/06 , G06F5/14 , G06F12/02 , G06F12/08 , G06F13/00 , G06F13/14 , G06F13/16 , G06F13/38
Abstract: PROBLEM TO BE SOLVED: To provide a bandwidth maintenance queue manager for (first-in first-out)FIFO buffer provided with another DRAM storage device for maintaining a FIFO queue. SOLUTION: A FIFO buffer is used on an ASIC chip so that plural queue entries can be stored and retrieved. As long as the total size of queues does not exceed a usable storage device in the buffer, any data storage device is not required more. When supplied data exceeds the buffer storage space of a certain prescribed quantity in the FIFO buffer, however, these data are written in the other data storage device in the form of packet and read from that storage device. That packet has an optimal size for maintaining the peak performance of the data storage device and is written in the data storage device in a way such as queuing with the address sequence of FIFO.
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公开(公告)号:JP2002024293A
公开(公告)日:2002-01-25
申请号:JP2001104687
申请日:2001-04-03
Applicant: IBM
Inventor: CALVIGNAC JEAN LOUIS , HEDDES MARCO C , JEFFERIES CLARK DEBUS , PATEL PIYUSH CHUNILAL , RINALDI MARK ANTHONY
Abstract: PROBLEM TO BE SOLVED: To provide a new data structure, a method, and a device for a software management tree(SMT) which provide a control point processor. SOLUTION: This retrieving mechanism reduces the storage space of a node by using only a forward pointer together with a next bit or bit group to be tested next. Multiple retrieval is unnecessary and filter rules for an application are processed to make it possible to connect various filter rules. Two patterns of the same length are stored in respective leaves to define range comparison. Final comparing operation is comparison within a range or comparison below a mask. Through the comparison within the range, it is decided whether or not an input key is within the range defined by the two patterns. Through the comparison below the mask, various bits in the input key are compared with various bits in a 1st leaf pattern under the mask specified with the 2nd leaf pattern.
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公开(公告)号:JP2001350638A
公开(公告)日:2001-12-21
申请号:JP2001104520
申请日:2001-04-03
Applicant: IBM
Inventor: DAVIS GORDON TAYLOR , HEDDES MARCO C , LEAVENS ROSS BOYD , VERPLANKEN FABRICE JEAN
Abstract: PROBLEM TO BE SOLVED: To attain the more efficient use of a processor resource. SOLUTION: When an execution is permitted in a thread that is stopping the acting, a prefetch buffer 118 is used in relation to a plurality of independent thread processings in a method as avoids an instantaneous stop. In order to realize the more efficient use of the processor resource, a mechanism 30 for controlling the switching from the thread within a processor to another thread is established. This mechanism imparts a temporary control to the alternative execution thread when a short waiting time event is generated, and imparts a perfect control to the alternative execution thread when a long waiting time even is generated. This thread control mechanism comprises a priority FIFO constituted so that the execution priorities of at least two execution threads within the processor are controlled according to their outputs on the basis of the length of the time when each execution thread is stayed within an FIFO 52.
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公开(公告)号:JP2001222465A
公开(公告)日:2001-08-17
申请号:JP2000390789
申请日:2000-12-22
Applicant: IBM
Inventor: BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO C , JENKINS STEVEN KENNETH , SIEGEL MICHAEL STEVEN , MICHAEL RAYMOND TROMBLAY , VERPLANKEN FABRICE JEAN
IPC: G06F12/06 , G06F12/00 , G06F12/02 , G06F13/00 , G06F13/16 , G06F15/167 , G11C11/407 , H04L12/56
Abstract: PROBLEM TO BE SOLVED: To improve the capacity of a network processor for moving data to a dynamic random access memory(DRAM) chip to be used for a computer system or moving data from the chip. SOLUTION: Two double data rate DRAMs are used in order to double band width in accordance with the throughput of increased data. The movement of data is further improved by setting up complete reading of four banks and complete writing of four banks by a network processor in each repeat of a DRAM time clock. A scheme for reading and writing accesses randomized by the network processor is discloses. The scheme can be applied especially to a network such as the Ethernet (R) using various frame sizes.
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