公开(公告)号：US3728592A

公开(公告)日：1973-04-17

申请号：US3728592D

申请日：1971-09-14

Applicant: IBM

Inventor： JOSHI M ,  TSU HSING YEH ,  MASTERS B ,  VIVA O

IPC: H01L21/00 ,  H01L21/8222 ,  H01L7/44 ,  H01L9/12 ,  H01L19/00

CPC classification number: H01L21/8222 ,  H01L21/00 ,  Y10S438/904

Abstract: A method of fabricating high-speed planar transistor structures by reducing carrier lifetime through doping with carrier lifetime killers. Gold is diffused through the front surface of the silicon structure during transistor fabrication. The gold is introduced from the vapor phase in a controlled manner so that its solid solubility in silicon is not exceeded. A simultaneous gold and base diffusion is preferred. Such a simultaneous diffusion produces a novel planar transistor structure having a gold distribution curve with an unexpected increased concentration peak in the region proximate to the basecollector junction.

Abstract translation: 一种制造高速平面晶体管结构的方法，通过掺杂载流子寿命抑制剂减少载流子寿命。 在晶体管制造期间，金通过硅结构的前表面扩散。 以受控的方式从气相中引入金，使得其在硅中的固溶度不被超过。 同时的金和碱扩散是优选的。