公开(公告)号：DE3072186D1

公开(公告)日：1991-02-14

申请号：DE3072186

申请日：1980-05-29

Applicant: IBM

Inventor： SCHORR HERBERT ,  WALDAWSKY-BERGER IRVING

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

Abstract: In a computer system the operating speed is increased by increasing the number of general registers (4) with a plurality of implicit registers (9) in an associative memory (3). An instruction (6) generated in a processing unit (1) for data access provides parameter words, such as base and displacement words, to be used as search arguments for an associative search for data in the implicit registers. If a match occurs, the data from the selected register is transferred to the processing unit (1) and the address generation started by the instruction for a memory (2) access is terminated.