公开(公告)号：US3577190A

公开(公告)日：1971-05-04

申请号：US3577190D

申请日：1968-06-26

Applicant: IBM

Inventor： COCKE JOHN ,  DAUBER PHILIP S ,  SCHORR HERBERT ,  SUSSENGUTH EDWARD H

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/10

CPC classification number: G06F9/30069

Abstract: Apparatus in a digital computer for allowing the skipping of predetermined instructions in a sequence of instructions is disclosed. Means are provided for detecting a specific type of instruction in a sequence of instructions. This specific type of instruction is referred to as a skip instruction and indicates that upon the occurrence of a specified machine condition, predetermined subsequent instructions in said sequence are to be skipped. Further means are provided to determine the occurrence of the specified machine condition, and to emit an output signal indicative of the occurrence. Means responsive to the output signal effect the skipping of the predetermined instructions.

公开(公告)号：US3670309A

公开(公告)日：1972-06-13

申请号：US3670309D

申请日：1969-12-23

Applicant: IBM

Inventor： AMDAHL GENE M ,  ARNOLD RICHARD F ,  DAUBER PHILIP S ,  FREIMAN CHARLES V ,  ROBELEN RUSSELL J ,  SCHORR HERBERT ,  WIERZBICKI JOHN R

IPC: G06F13/10 ,  G06F12/08 ,  G06F13/18 ,  G11C9/00 ,  G06F13/00

CPC classification number: G06F12/0857 ,  G06F13/18

Abstract: Described is a storage control system for a two-level storage system. The system includes a high-speed storage against which requests for data are processed and a slower, larger-capacity main storage. Requests for data are received in terms of logical addresses. Requests can be received concurrently at a plurality of request ports where they are buffered in request stacks. A tag storage serves as an index to the data currently resident in high-speed storage, and a directory storage acts as an index to data currently in main storage. A sequence interlock generator is included which interlocks requests in the plurality of request stacks to insure that requests to the same storage area are performed in proper sequence to insure data integrity. When a request is serviced, the logical address is transformed into a plurality of physical addresses in high-speed storage. The corresponding tags from the tag storage and the corresponding data from the high-speed storage are concurrently fetched. A comparison is made of the tags with the transformed address to determine whether the requested data is in high-speed storage. Since request to the same storage entity in high-speed storage or tag storage can be made concurrently by all request ports, conflict resolvers are included to resolve conflicts arising from simultaneous requests to either of these two storages. High-speed storage is divided into storage modules capable of simultaneous operation such that requests from the plurality of request ports can be serviced concurrently. If comparison of the tags indicate that the requested data is available, the request is serviced. An interstorage transfer mechanism is included such that if the requested data is not available in high-speed storage, then the data is retrieved from main storage and placed into high-speed storage for subsequent processing of the request. Concurrently with interstorage transfer, processing of other requests from the request ports is permissible. In the replacement of data from main storage to high-speed storage, provision is made for also replacing data from high-speed storage to main storage if such be necessary.

公开(公告)号：US3577189A

公开(公告)日：1971-05-04

申请号：US3577189D

申请日：1969-01-15

Applicant: IBM

Inventor： COCKE JOHN ,  RANDELL BRIAN ,  SCHORR HERBERT ,  SUSSENGUTH EDWARD H

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/00 ,  G06F9/16

CPC classification number: G06F9/3846

Abstract: Apparatus and a method in a digital computer is disclosed for allowing improved program branching from a first instruction sequence to a second instruction sequence. Said apparatus includes means for decoding a branch instruction in said first sequence; means for determining parameters which are to enter into a condition determination, the resolution of which defines whether or not the branch is to be made, means for detecting a specific type instruction in said first sequence subsequent to said branch instruction, said specific type instruction indicative of the point in the first instruction sequence at which the branch is to be made; and means responsive to said detection for ordering instructions from said second instruction sequence to be processed subsequent to the processing of said specific type instruction.

公开(公告)号：DE2001664A1

公开(公告)日：1970-07-23

申请号：DE2001664

申请日：1970-01-15

Applicant: IBM

Inventor： COCKE JOHN ,  RANDELL BRIAN ,  SCHORR HERBERT ,  HENRY SUSSENGUTH EDWARD

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/16

Abstract: 1282341 Data processing INTERNATIONAL BUSINESS MACHINES CORP 12 Jan 1970 [15 Jan 1969] 1358/70 Heading G4A In stored-program data processing apparatus, switching to another instruction stream as a result of a successful conditional branch instruction occurs after execution of a marker instruction. Instructions are accessed from memory and inserted into the top of a multi-instruction pushdown buffer together with bits indicating, for each instruction, whether or not it is a target, branch or exit instruction. The target bit is provided at the memory (see below) and the branch and exit bits are derived by a predecoder. The instruction at the bottom of the buffer is decoded. If it is a branch instruction, two fields in it select two bits from a condition register and 1 of 8 logical functions of these specified by part of the op code is evaluated in a function generator to determine whether the branch should be taken, the branching being to an address obtained by adding a field from the instruction and the contents of one of a plurality of registers selected by another field of the instruction. However, the sequence of instruction fetching branches to this address only when the next exit instruction enters the buffer. The branched-to instruction has its target bit set to 1 at the memory. Decoding and therefore execution of each instruction in the buffer between the exit instruction and the target instruction is inhibited, the inhibition terminating when the target instruction is shifted into the bottom position of the buffer, in response to the target bit of 1. Decoding of any branch instruction after a successful branch instruction and before the next exit instruction is also inhibited. If both an exit and a branch instruction are present in the buffer but a successful branch has not been determined, instruction fetching is suspended until not all these conditions exits, thus awaiting the result of the branch test. Instruction fetching is from the next sequential address if there is no exit instruction in the buffer, and if there is but there is neither a branch instruction in the buffer nor an indication of a successful branch determined.

公开(公告)号：DE3072186D1

公开(公告)日：1991-02-14

申请号：DE3072186

申请日：1980-05-29

Applicant: IBM

Inventor： SCHORR HERBERT ,  WALDAWSKY-BERGER IRVING

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

Abstract: In a computer system the operating speed is increased by increasing the number of general registers (4) with a plurality of implicit registers (9) in an associative memory (3). An instruction (6) generated in a processing unit (1) for data access provides parameter words, such as base and displacement words, to be used as search arguments for an associative search for data in the implicit registers. If a match occurs, the data from the selected register is transferred to the processing unit (1) and the address generation started by the instruction for a memory (2) access is terminated.

公开(公告)号：IT1151066B

公开(公告)日：1986-12-17

申请号：IT2260680

申请日：1980-06-06

Applicant: IBM

Inventor： SCHORR HERBERT ,  WLADAWSKY-BERGER IRVING

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/38 ,  G06F12/08 ,  G11B

Abstract: In a computer system the operating speed is increased by increasing the number of general registers (4) with a plurality of implicit registers (9) in an associative memory (3). An instruction (6) generated in a processing unit (1) for data access provides parameter words, such as base and displacement words, to be used as search arguments for an associative search for data in the implicit registers. If a match occurs, the data from the selected register is transferred to the processing unit (1) and the address generation started by the instruction for a memory (2) access is terminated.

公开(公告)号：IT8022606D0

公开(公告)日：1980-06-06

申请号：IT2260680

申请日：1980-06-06

Applicant: IBM

Inventor： SCHORR HERBERT ,  WLADAWSKY-BERGER IRVING

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/38 ,  G06F12/08 ,  G11B

Abstract: In a computer system the operating speed is increased by increasing the number of general registers (4) with a plurality of implicit registers (9) in an associative memory (3). An instruction (6) generated in a processing unit (1) for data access provides parameter words, such as base and displacement words, to be used as search arguments for an associative search for data in the implicit registers. If a match occurs, the data from the selected register is transferred to the processing unit (1) and the address generation started by the instruction for a memory (2) access is terminated.