公开(公告)号：DE3584402D1

公开(公告)日：1991-11-21

申请号：DE3584402

申请日：1985-06-19

Applicant: IBM

Inventor： WALDECKER DONALD EMIL ,  WRIGHT CHARLES GORDON

IPC: G06F13/36 ,  G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F15/16 ,  G06F13/18

Abstract: A plurality of data processor units (11, 16 17) are connected to a common bus (10) which is connected to first and second interleaved storage units (1, 2). The system is a synchronous one in which timing means (23) establish a series of information transfer intervals (t0-t7, etc.). One or more of the processors units (16, 17) contain apparatus for selectively commencing an address transfer on the bus (10) to one of the storage units (1, 2) during a transfer interval; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors (16. 17) have means (3, 4) for monitoring the bus (10) in order to determine whether an address on the bus has been transferred to the first or the second storage unit (1.2) during a particular transfer interval. The address transfer apparatus further includes apparatus (50) responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units (1, 2) to thus achieve alternating interleaving between storage units (1, 2).