公开(公告)号：JP2000216386A

公开(公告)日：2000-08-04

申请号：JP2000012253

申请日：2000-01-20

Applicant: IBM

Inventor： MA WILLIAM HSIOH-LIEN ,  WANN HSING-JEN C

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/336 ,  H01L27/08 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To fabricate an extremely shallow junction by forming a first insulation sidewall spacer on the sidewall in the gate region of a semiconductor substrate, forming a second insulation spacer in the first insulation spacer and then silicificating the upper surface of the source-drain region. SOLUTION: An insulation layer 2, a conductive layer 3 and a second insulation layer 4 are provided sequentially on a semiconductor substrate 1. The second insulation layer 4 and the conductive layer 3 are then etched and a selected part is removed and a third insulation layer 5 is provided thereon. Subsequently, the insulation layer 2 and the third insulation layer 5 are removed while leaving the insulator on the sidewall of the conductive layer 3 as a gate, thus forming an insulation sidewall spacer 9 on the sidewall of the gate conductive layer 3. Thereafter, a second insulation spacer 10 is formed on the sidewall spacer 9 and the part there not covered with the second insulation spacer 10 is removed. Finally, the source-drain region is silicified to form a metal silicide 12.

公开(公告)号：JP2005197753A

公开(公告)日：2005-07-21

申请号：JP2005002906

申请日：2005-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN C ,  KWON HON WON

IPC: H01L21/335 ,  H01L21/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28194 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device gate structure having an internal spacer.
SOLUTION: The manufacturing method includes replacement gate process, in which a part of a substrate is exposed by removing material in a gate region, gate dielectric is formed on an exposed portion of the substrate, and an internal spacer layer which covers the gate dielectric and dielectric material is formed. Next, a silicon layer which covers the internal spacer layer is formed. Next, the formed structure is planarized, and a part of the silicon layer and a part of the internal spacer layer are made to remain in the gate region. Next, a silicide gate structure is formed by using the silicon, and the silicide gate structure is separated from the dielectric material around the gate with the internal spacer layer. The semiconductor device can include a first gate region and a second gate region, between which an interface covered by the internal spacer layer is formed. When the device has two gate regions, separate silicide structures, which are separated with the internal spacer layer, can be generated by applying the above process to both the gate regions.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种具有内部间隔物的半导体器件栅极结构的制造方法。 解决方案：制造方法包括替换栅极工艺，其中通过去除栅极区域中的材料使衬底的一部分暴露，栅极电介质形成在衬底的暴露部分上，并且内部间隔层覆盖 形成栅介质和电介质材料。 接下来，形成覆盖内部间隔层的硅层。 接下来，形成的结构被平坦化，并且使硅层的一部分和内部间隔层的一部分保留在栅极区域中。 接下来，通过使用硅形成硅化物栅极结构，并且利用内部间隔层将硅化物栅极结构与栅极周围的电介质材料分离。 半导体器件可以包括第一栅极区域和第二栅极区域，在其间形成由内部间隔层覆盖的界面。 当器件具有两个栅极区域时，可以通过将上述过程应用于两个栅极区域来产生与内部间隔层分离的分离的硅化物结构。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005197748A

公开(公告)日：2005-07-21

申请号：JP2005001988

申请日：2005-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN C

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66583 ,  H01L21/28079 ,  H01L21/28247 ,  H01L21/823835 ,  H01L29/66545

Abstract: PROBLEM TO BE SOLVED: To provide a method of producing one metal replacement gate or two metal replacement gate for a semiconductor device.
SOLUTION: This structure contains silicide contacts with a gate region. A part of a substrate is exposed, by removing a dummy gate structure and a sacrificial gate dielectric, and a gate dielectric is formed on the exposed part. A metal layer is formed so as to cover the gate dielectric and dielectric materials. This metal layer, if it is convenient, can be made of a blanket metal layer covering a device wafer. Next, a silicon layer is formed so as to cover the metal layer. This layer can be also made of a blanket layer. Next, the top face of the dielectric materials is exposed, by performing flatting or etch back process. Other parts of the metal layer and the silicon layer remain in a gate region 11, and there is provided a front surface, having the same plane as the top face of the dielectric materials. Next, there are formed the silicide contacts, which are in contact with the metal layer in the gate region 11.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于半导体器件的一个金属替换栅极或两个金属替代栅极的制造方法。 解决方案：该结构包含与栅极区域的硅化物接触。 通过去除伪栅极结构和牺牲栅极电介质来暴露衬底的一部分，并且在暴露部分上形成栅极电介质。 形成金属层以覆盖栅介质和电介质材料。 如果方便，该金属层可以由覆盖器件晶片的覆盖金属层制成。 接下来，形成硅层以覆盖金属层。 该层也可以由覆盖层制成。 接下来，通过进行平坦化或回蚀加工，使电介质材料的顶面露出。 金属层和硅层的其它部分保留在栅极区域11中，并且设置有与电介质材料的顶面相同平面的前表面。 接下来，形成与栅极区域11中的金属层接触的硅化物触点。版权所有（C）2005，JPO＆NCIPI

公开(公告)号：DE10002121A1

公开(公告)日：2000-08-03

申请号：DE10002121

申请日：2000-01-20

Applicant: IBM

Inventor： MA WILLIAM HSIAOH-LIEN ,  WANN HSING-JEN C

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/336 ,  H01L27/08 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.

公开(公告)号：DE10002121B4

公开(公告)日：2006-01-12

申请号：DE10002121

申请日：2000-01-20

Applicant: IBM

Inventor： MA WILLIAM HSIAOH-LIEN ,  WANN HSING-JEN C

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/336 ,  H01L27/08 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.