公开(公告)号：JP2001237370A

公开(公告)日：2001-08-31

申请号：JP2000396941

申请日：2000-12-27

Applicant: IBM

Inventor： MA WILLIAM HSIOH-LIEN ,  SCHEPIS DOMINIC JOSEPH

IPC: H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L27/00 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a three-dimensional multilayer element which does not require minute alignment. SOLUTION: A multilayer three-dimensional semiconductor structure includes a first semiconductor substrate and the structure 4 of a first level, which constitutes a first active element. The structure 9 of a second level, which constitutes an SOI semiconductor structure, is connected to the structure of the first level and is constitutes a second active element. The first active element is superior in heat resistance compared to the second active element in the design of the element.

公开(公告)号：JP2000216386A

公开(公告)日：2000-08-04

申请号：JP2000012253

申请日：2000-01-20

Applicant: IBM

Inventor： MA WILLIAM HSIOH-LIEN ,  WANN HSING-JEN C

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/336 ,  H01L27/08 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To fabricate an extremely shallow junction by forming a first insulation sidewall spacer on the sidewall in the gate region of a semiconductor substrate, forming a second insulation spacer in the first insulation spacer and then silicificating the upper surface of the source-drain region. SOLUTION: An insulation layer 2, a conductive layer 3 and a second insulation layer 4 are provided sequentially on a semiconductor substrate 1. The second insulation layer 4 and the conductive layer 3 are then etched and a selected part is removed and a third insulation layer 5 is provided thereon. Subsequently, the insulation layer 2 and the third insulation layer 5 are removed while leaving the insulator on the sidewall of the conductive layer 3 as a gate, thus forming an insulation sidewall spacer 9 on the sidewall of the gate conductive layer 3. Thereafter, a second insulation spacer 10 is formed on the sidewall spacer 9 and the part there not covered with the second insulation spacer 10 is removed. Finally, the source-drain region is silicified to form a metal silicide 12.

公开(公告)号：JPH11289069A

公开(公告)日：1999-10-19

申请号：JP1527799

申请日：1999-01-25

Applicant: IBM

Inventor： HORAK DAVID VACLAV ,  FURUKAWA TOSHIHARU ,  HOLMES STEVEN JOHN ,  HAKEY MARK CHARLES ,  MA WILLIAM HSIOH-LIEN ,  MANDELMAN JACK ALLAN

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To integrate a step move element adjacent to a deep trench capacitor by arranging an FET on one portion of the deep trench capacitor in a substrate, and providing an insulation region with a larger depth than the FET while surrounding the FET. SOLUTION: An FET is arranged on one portion of a deep trench capacitor 13 in a substrate, a travel element gate 17 is arranged on one portion of the deep trench capacitor 13 in the FET, and an n+ diffusion region 23 being separated from the travel element gate 17 by the insulation layer is formed adjacent to the side part of the travel element gate 17. Also, an isolation region 15 being insulated from the travel element gate 17 of the FET is arranged on one portion of the deep trench capacitor that is not covered with the FET, surrounds the FET and is located in the substrate, thus forming a larger depth than the FET and hence integrating the step travel element adjacent to the deep trench capacitor 13.

公开(公告)号：DE2966185D1

公开(公告)日：1983-10-27

申请号：DE2966185

申请日：1979-07-31

Applicant: IBM

Inventor： MA WILLIAM HSIOH-LIEN

IPC: G03F7/00 ,  G03F7/26 ,  G03F7/38 ,  G03F7/40 ,  H01L21/027 ,  H05K3/06 ,  G03F7/02

Abstract: An organic polymer resist image layer, formed on a substrate, is stabilized by placing the substrate with the resist image layer in an electrodeless glow discharge in a low pressure fluorine containing atmosphere, for example, CF4, so as to harden the exposed surface of the layer and then heating the layer.

公开(公告)号：DE2715982A1

公开(公告)日：1977-11-17

申请号：DE2715982

申请日：1977-04-09

Applicant: IBM

Inventor： MA TSO-PING ,  MA WILLIAM HSIOH-LIEN

IPC: H01L21/324 ,  H01L21/265 ,  H01L21/326 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/30 ,  H03H3/00

Abstract: The electrical properties of MIS semiconductor devices, which have been damaged by radiation, are restored by treating the devices in a properly oriented RF field at low pressure.

公开(公告)号：DE3267357D1

公开(公告)日：1985-12-19

申请号：DE3267357

申请日：1982-03-12

Applicant: IBM

Inventor： FRIESER RUDOLF GRUENSPAN ,  MA WILLIAM HSIOH-LIEN ,  OZOLS GUNARS MIERVALDIS ,  ZINGERMAN BRYANT NILS

IPC: C23F4/00 ,  H01J37/34 ,  H01L21/302 ,  H01L21/3065 ,  H01J37/08 ,  H01J37/32 ,  C23C14/00

Abstract: A cathode for reactive ion etching is provided which improves the etch rate and the uniformity of etching on the object etched. The cathode (10) has a quartz plate (12) with a series of recesses (14) having disks (16) therein of Si, C, Al, W, Cr, Ti or Mo, in particular the same material as the object to be etched, and a ring (18) of preferably that same material around the outer edge of the plate (12). In one embodiment a cathode for etching silicon wafers has silicon disks recessed in a quartz plate at each wafer holding position and a ring of silicon around the outer edge of the plate.