FABRICATION OF SEMICONDUCTOR DEVICE HAVING JUNCTION

    公开(公告)号:JP2000216386A

    公开(公告)日:2000-08-04

    申请号:JP2000012253

    申请日:2000-01-20

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To fabricate an extremely shallow junction by forming a first insulation sidewall spacer on the sidewall in the gate region of a semiconductor substrate, forming a second insulation spacer in the first insulation spacer and then silicificating the upper surface of the source-drain region. SOLUTION: An insulation layer 2, a conductive layer 3 and a second insulation layer 4 are provided sequentially on a semiconductor substrate 1. The second insulation layer 4 and the conductive layer 3 are then etched and a selected part is removed and a third insulation layer 5 is provided thereon. Subsequently, the insulation layer 2 and the third insulation layer 5 are removed while leaving the insulator on the sidewall of the conductive layer 3 as a gate, thus forming an insulation sidewall spacer 9 on the sidewall of the gate conductive layer 3. Thereafter, a second insulation spacer 10 is formed on the sidewall spacer 9 and the part there not covered with the second insulation spacer 10 is removed. Finally, the source-drain region is silicified to form a metal silicide 12.

    TRENCH STORAGE DRAM CELL CONTAINING STEP TRAVEL ELEMENT AND ITS FORMATION METHOD

    公开(公告)号:JPH11289069A

    公开(公告)日:1999-10-19

    申请号:JP1527799

    申请日:1999-01-25

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To integrate a step move element adjacent to a deep trench capacitor by arranging an FET on one portion of the deep trench capacitor in a substrate, and providing an insulation region with a larger depth than the FET while surrounding the FET. SOLUTION: An FET is arranged on one portion of a deep trench capacitor 13 in a substrate, a travel element gate 17 is arranged on one portion of the deep trench capacitor 13 in the FET, and an n+ diffusion region 23 being separated from the travel element gate 17 by the insulation layer is formed adjacent to the side part of the travel element gate 17. Also, an isolation region 15 being insulated from the travel element gate 17 of the FET is arranged on one portion of the deep trench capacitor that is not covered with the FET, surrounds the FET and is located in the substrate, thus forming a larger depth than the FET and hence integrating the step travel element adjacent to the deep trench capacitor 13.

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