公开(公告)号：JP2001352077A

公开(公告)日：2001-12-21

申请号：JP2001113487

申请日：2001-04-12

Applicant: IBM

Inventor： WILLIAM R DAKUTERA ,  JOSHI RAJIV V ,  WARNER A ROUCH

IPC: H01L27/11 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To obtain a method for forming an SOI FET constituting an SRAM cell, in which local body effect resistance of the SRAM cell is improved. SOLUTION: An SRAM cell has an SOI/bulk hybrid structure, where source/ drain diffusion regions 206, 208 have not reached an underlying insulator layer 212. Consequently, an FET having a body (substrate) contact 216 for deep diffusion regions, i.e., P-type diffusion regions 206, 208, across the total thickness of an island 210 can be formed on the surface of an SOI layer 210 and a passage 211 is left beneath the diffusion regions 206, 208. The FET is located on an embedded oxide (BOX) layer 212 and formed into an SOI silicon island 210 insulated by STI(shallow trench isolation). A bit line diffusion region, shared by SRAM cells on adjacent word lines, may also be made a deep diffusion region.