公开(公告)号：EP1652235A4

公开(公告)日：2008-09-17

申请号：EP04757122

申请日：2004-07-19

Applicant: IBM

Inventor： JOSHI RAJIV V ,  WILLIAMS RICHARD Q

IPC: H01L29/786 ,  H01L20060101 ,  H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/11 ,  H01L27/12 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

Abstract: A channel (16) of a FinFET (10) has a channel core (24) and a channel envelope (32), each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78

公开(公告)号：EP2255381A4

公开(公告)日：2012-03-07

申请号：EP09704712

申请日：2009-01-23

Applicant: IBM

Inventor： JOSHI RAJIV V ,  HSU LOIUS LU-CHEN ,  WANG PING-CHUAN ,  YANG ZHIJIAN

IPC: H01L21/337 ,  G11C7/12 ,  G11C11/12 ,  G11C11/404 ,  G11C11/412

CPC classification number: G11C29/04 ,  G11C7/12 ,  G11C11/412

公开(公告)号：JP2005117037A

公开(公告)日：2005-04-28

申请号：JP2004283447

申请日：2004-09-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAN YUEN H ,  LEWIS L SUU ,  JOSHI RAJIV V ,  WONG ROBERT CHI-FOON

IPC: G11C11/41 ,  G11C11/00 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11

CPC classification number: G11C11/412

Abstract: PROBLEM TO BE SOLVED: To provide a method for designing a 6T SRAM cell having greater stability and/or a smaller cell size.
SOLUTION: A 6T SRAM cell has a pair of access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic "0" during access of the cell thereby increasing the stability of the cell, especially for cells during "half select". Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without affecting the stability of the cell during access. And, by decreasing the cell size, the overall design layout area of a chip may also be decreased.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种设计具有更大稳定性和/或更小单元尺寸的6T SRAM单元的方法。 解决方案：6T SRAM单元具有一对存取晶体管（NFET），一对上拉晶体管（PFET）和一对下拉晶体管（NFET），其中存取晶体管具有较高的阈值 电压低于下拉晶体管，这使得SRAM单元在单元访问期间有效地保持逻辑“0”，从而增加了单元的稳定性，特别是对于“半选择”期间的单元。 此外，可以减小下拉晶体管的沟道宽度，从而降低高性能六晶体管SRAM单元的尺寸，而不会影响存取期间单元的稳定性。 而且，通过减小单元尺寸，芯片的总体设计布局面积也可能降低。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2005010944A3

公开(公告)日：2005-08-11

申请号：PCT/US2004023183

申请日：2004-07-19

Applicant: IBM ,  JOSHI RAJIV V ,  WILLIAMS RICHARD Q

Inventor： JOSHI RAJIV V ,  WILLIAMS RICHARD Q

IPC: H01L20060101 ,  H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/11 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

Abstract: A channel (16) of a FinFET (10) has a channel core (24) and a channel envelope (32), each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78

Abstract translation: FinFET（10）的沟道（16）具有沟道芯（24）和沟道包络（32），每个沟道包络由限定不同晶格结构的半导体材料制成以利用应变硅特性。 栅极通过栅极电介质耦合到沟道外壳。 示例性的材料是Si和SixGe1-x，其中78

公开(公告)号：JP2006203198A

公开(公告)日：2006-08-03

申请号：JP2006007461

申请日：2006-01-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JOSHI RAJIV V ,  WACHNIK RICHARD A ,  TAN YUE ,  KERRY BERNSTEIN

IPC: H01L27/11 ,  H01L21/8244 ,  H01L27/10

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM memory and a microprocessor, comprising a logic portion formed on a silicon substrate and an SRAM array portion. SOLUTION: The SRAM array has a body region, where at least one pair of neighboring NFETs of the SRAM cell is linked in a leakage path diffusion region 338 under shallow source/drain region 334, the leakage path diffusion region extends from the bottom of the source/drain diffusion to an embedded oxide layer 320; and at least one pair of PFETs of the neighboring SRAM cells has a body region 336, linked in a similar leakage path diffusion region under neighboring source/drain diffusion. The logic circuit portion of the microprocessor has a floating body region and an NFET, formed in a crystal orientation SOI silicon region 330 and a PFET formed in a crystal orientation bulk silicon region, and the SRAM memory portion has an NFET, formed in the crystal orientation SOI silicon region and a PFET formed in the crystal orientation silicon region. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种SRAM存储器和微处理器，包括形成在硅衬底上的逻辑部分和SRAM阵列部分。 解决方案：SRAM阵列具有主体区域，其中SRAM单元的至少一对相邻NFET被连接在浅源/漏区334下方的泄漏路径扩散区域338中，泄漏路径扩散区域从 源/漏扩散的底部到嵌入的氧化物层320; 并且相邻SRAM单元的至少一对PFET具有主体区域336，其连接在相邻的源极/漏极扩散部下的类似泄漏路径扩散区域中。 微处理器的逻辑电路部分具有形成在晶体取向SOI硅区域330和形成于晶体取向体硅区域中的PFET的浮体区域和NFET，并且SRAM存储器部分具有形成在晶体中的NFET 取向SOI硅区域和形成在晶体取向硅区域中的PFET。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005072599A

公开(公告)日：2005-03-17

申请号：JP2004244046

申请日：2004-08-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BHAVNAGARWALA AZEEZ ,  JOSHI RAJIV V ,  KOSONOCKY STEPHEN V

IPC: G11C11/418 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11

CPC classification number: G11C11/412

Abstract: PROBLEM TO BE SOLVED: To provide an unloaded 4T SRAM cell and a method for operating the SRAM cell.
SOLUTION: The unloaded 4T SRAM cell 20 comprises a pair of access transistors (N1 and N2) and a pair of pull-down transistors (N3 and N4), all of which are implemented as N-channel transistors (NFETs or NMOSFETs). The access transistors have threshold voltages (Vt) lower than those of the pull-down transistors, which enables the SRAM cell to effectively maintain a logic "1" potential during standby. The pull-down transistors have channel widths greater than those of the access transistors, which enables the SRAM cell to effectively maintain a logic "0" potential at a given storage node during read operation.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一个无负载的4T SRAM单元和一个操作SRAM单元的方法。 解决方案：卸载的4T SRAM单元20包括一对存取晶体管（N1和N2）和一对下拉晶体管（N3和N4），所有这些都被实现为N沟道晶体管（NFET或NMOSFET） ）。 存取晶体管具有低于下拉晶体管的阈值电压（Vt），这使得SRAM单元能够在待机期间有效地保持逻辑“1”电位。 下拉晶体管的沟道宽度大于存取晶体管的沟道宽度，这使得SRAM单元能够在读取操作期间在给定存储节点处有效地保持逻辑“0”电位。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005150731A

公开(公告)日：2005-06-09

申请号：JP2004328193

申请日：2004-11-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JOSHI RAJIV V ,  HSU LOUIS C ,  HOOK TERENCE B ,  RAUSCH WERNER

IPC: H01L21/76 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823892 ,  H01L27/0928

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS well structure and a method for forming it.
SOLUTION: A method for forming a CMOS well structure comprises a process of forming multiple first conductivity type wells over a substrate. The multiple first conductivity type wells are formed in respective openings in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on the sidewalls of each of the first conductivity type wells. Multiple second conductivity type wells are formed in respective areas between the first conductivity type wells. Multiple shallow trench isolations are formed between the first conductivity type wells and the second conductivity type wells. The multiple first conductivity type wells are formed in a first selective epitaxial growth process, and the multiple second conductivity type wells are formed in a second selective epitaxial growth process.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种CMOS阱结构及其形成方法。 解决方案：用于形成CMOS阱结构的方法包括在衬底上形成多个第一导电类型阱的工艺。 在第一掩模中的相应开口中形成多个第一导电类型的阱。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电型孔的侧壁上形成侧壁间隔物。 在第一导电型孔之间的相应区域中形成多个第二导电类型的阱。 在第一导电类型阱和第二导电类型阱之间形成多个浅沟槽隔离。 在第一选择性外延生长工艺中形成多个第一导电型阱，并且在第二选择性外延生长工艺中形成多个第二导电型阱。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004185799A

公开(公告)日：2004-07-02

申请号：JP2003396226

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUANG CHING-TE K ,  JOSHI RAJIV V ,  ROSENFIELD MICHAEL G

IPC: G11C11/412 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/11

CPC classification number: G11C11/412

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption of an integrated circuit without exerting an influence on the circuit performance.
SOLUTION: The integrated circuit capable of including such an array as static RAM (SRAM) provided with a high threshold array device for reducing leakage and other selected devices is provided. The high threshold device has a thick-formed gate oxide film or a high-k dielectric gate oxide film. The high-threshold device is also used for a non-core circuit like a test circiut. Moreover, an acritical path is discriminated, and an acritical path margin is discriminated. A device threshold higher than specified is selected for an FET of the acritical path based on the acritical path mergin. Delay in the acritical path is re-checked; the FET of the acritical path satisfactory at the re-checking is formed of the thickened gate oxide film, and unselected FETs are formed in normal gate oxide film thickness.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2001352077A

公开(公告)日：2001-12-21

申请号：JP2001113487

申请日：2001-04-12

Applicant: IBM

Inventor： WILLIAM R DAKUTERA ,  JOSHI RAJIV V ,  WARNER A ROUCH

IPC: H01L27/11 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To obtain a method for forming an SOI FET constituting an SRAM cell, in which local body effect resistance of the SRAM cell is improved. SOLUTION: An SRAM cell has an SOI/bulk hybrid structure, where source/ drain diffusion regions 206, 208 have not reached an underlying insulator layer 212. Consequently, an FET having a body (substrate) contact 216 for deep diffusion regions, i.e., P-type diffusion regions 206, 208, across the total thickness of an island 210 can be formed on the surface of an SOI layer 210 and a passage 211 is left beneath the diffusion regions 206, 208. The FET is located on an embedded oxide (BOX) layer 212 and formed into an SOI silicon island 210 insulated by STI(shallow trench isolation). A bit line diffusion region, shared by SRAM cells on adjacent word lines, may also be made a deep diffusion region.

公开(公告)号：JP2001308191A

公开(公告)日：2001-11-02

申请号：JP2001070099

申请日：2001-03-13

Applicant: IBM

Inventor： JOSHI RAJIV V ,  KARL E KREHL

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a computer program product concerning to design of the multi-input circuit, macro or chip, especially of an SOI circuit. SOLUTION: With regard to an multi-input circuit, an object list of items corresponding to a circuit device is generated. The items model local effect for a corresponding circuit element. The circuit is analyzed using static analysis or DC analysis and an initial local effect for the circuit device including body effect and local heat effect is obtained. The initial local effect is delivered to a circuit model for transient analysis. The local effect is inspected from inspected transient results and updated. Transient response is executed repetitively until variation of the local effect falls within an upper limit and the local effect is updated. In order to enhance efficiency, an unswitched device can be excluded from repetitive analysis and the analysis can be limited to a period where switching takes place.