公开(公告)号：JPH10301840A

公开(公告)日：1998-11-13

申请号：JP8892398

申请日：1998-04-01

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  WARREN EDWARD MALE ,  ROBERT DOMINIC MIRABERA ,  DAVID WAIN VICTOR

IPC: G06F12/04 ,  G06F5/00 ,  G06F7/76 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To transfer data between a power PC processor and an input/output device even when respective little endian byte orders are different by providing the power PC processor, the input/output device and a memory controller for transmitting the data between both of them. SOLUTION: This system is provided with a CPU 710 for using a power PC little endian byte order, an I/O adapter 718 for using a true little endian byte order and a memory controller sub system 501 for communicating the data between the CPU 710 and the I/O adapter 718. The memory controller sub system 501 converts the data transferred from the I/O adapter 718 to the CPU 710 or a memory 714 from the true one to the power PC little endian byte order. The data transferred from the CPU 710 or the memory 114 to the I/O adapter 718 are converted from the power PC one to the true little endian byte order.

公开(公告)号：JPH10340212A

公开(公告)日：1998-12-22

申请号：JP9145898

申请日：1998-04-03

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  WARREN EDWARD MALE

IPC: G06F11/30 ,  G06F11/22 ,  G06F13/00

Abstract: PROBLEM TO BE SOLVED: To make separable failure on a clock synchronous bus, by receiving an input to a shift register and shifting the contents of the shift register when detecting the driver of a data bus in the case of a bus error. SOLUTION: One bus driver and at least two devices are connected to each other and when a failure on the bus, which operates according to a bus clock 130, is separated, an input including a clock input 160 to an N-bit shift register 10 and a driver-enable signal 102 is received, and only when the clock input 160 is positive, the contents of the shift register 100 are shifted. A register 100 is latched corresponding to a detected error and the latched register 100 is scanned. Here, the clock input 160 further includes a system clock signal 130 and a check stop signal 140 and once the check stop signal 140 is received, the shift register clock 150 is stopped.