公开(公告)号：CA1223665A

公开(公告)日：1987-06-30

申请号：CA485188

申请日：1985-06-25

Applicant: IBM

Inventor： CHAITIN GREGORY J ,  HOPKINS MARTIN E ,  MARKSTEIN PETER W ,  WARREN HENRY S JR

IPC: G06F9/45 ,  G06F9/44

Abstract: GENERATING STORAGE REFERENCE INSTRUCTIONS IN AN OPTIMIZING COMPILER A method for improving the quality of code generated by a compiler in terms of execution time, object code space, or both. The method is applicable to computers that have a redundancy of instructions, in that the same operation exists in forms that operate between registers, between main storage locations, and between registers and main storage. The method selects the best form of each such instruction to use, for the context in which the instruction lies.

公开(公告)号：CA2123442A1

公开(公告)日：1995-03-21

申请号：CA2123442

申请日：1994-05-12

Applicant: IBM

Inventor： RAY DAVID S ,  THATCHER LARRY E ,  WARREN HENRY S JR

IPC: G06F9/38 ,  G06F15/16

Abstract: MULTIPLE EXECUTION UNIT DISPATCH WITH INSTRUCTION DEPENDENCY A multiple execution unit processing system is provided wherein each execution unit has an associated instruction buffer and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to executed in parallel on the execution units.