公开(公告)号：DE3380388D1

公开(公告)日：1989-09-14

申请号：DE3380388

申请日：1983-02-28

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WARREN RAYMOND HENRY ,  WESTCOTT DOUGLAS WAYNE

IPC: H03K3/037

Abstract: A hazard-free latch is disclosed comprising three NAND logic gates (1-3), one of the gates (3), in combination with its loading, being relatively fast and another of the gates (2), in combination with its output loading, being relatively slow. Both gates receive an input clock signal. Input data is applied to the third gate (1). The output of the fast gate (3) is connected to another input of the slow gate (2). The outputs of the third (1) and the slow gates (2) are connected to an output terminal and to another input of the fast gate (3).