公开(公告)号：DE3484147D1

公开(公告)日：1991-04-04

申请号：DE3484147

申请日：1984-03-30

Applicant: IBM

Inventor： WASSEL EDWARD RICHARD ,  WATKINS GERALD JOSEPH

IPC: G06F9/38 ,  G06F7/00 ,  G06F7/76 ,  G06F9/30 ,  G06F9/305 ,  G06F15/78 ,  G06F17/16

公开(公告)号：DE3750520D1

公开(公告)日：1994-10-20

申请号：DE3750520

申请日：1987-04-14

Applicant: IBM

Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

IPC: G06F9/22 ,  G06F15/16 ,  G06F17/16

Abstract: A method for optimizing performance in a fixed clock rate computer system. A control word is provided having a control portion for operational instructions and a programmable timing portion. The programmable timing portion includes a value representative of the sum of execution time and inter-execution delay time. A counter (22i) is provided for receiving the value representative of the execution and inter-execution times. The counter is capable of generating a signal (EOS) to indicate an end of decrementing operation. The operational instructions are executed simultaneously with the processing of the time value in the counter so that a subsequent instruction is executed only when an end of operation signal is received from the counter.

公开(公告)号：DE3584397D1

公开(公告)日：1991-11-21

申请号：DE3584397

申请日：1985-06-19

Applicant: IBM

Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

IPC: G11C19/00 ,  G01R31/317 ,  G01R31/3185 ,  H03K3/037

公开(公告)号：DE3686828D1

公开(公告)日：1992-11-05

申请号：DE3686828

申请日：1986-02-14

Applicant: IBM

Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

IPC: G06F17/16 ,  G06F15/80 ,  G06F15/347 ,  G06F15/76

Abstract: A parallel vector processor includes a plurality of vector registers, each vector register being subdivided into a plurality of smaller registers. A vector is stored in each vector register, the vector has a plurality of elements. The elements of the vector are assigned for storage in the smaller registers of the vector register. In the parallel vector processor, assume that each vector register is subdivided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers. The second and third successive M elements of the N element vector are each processed by the element processors 1 through M. As a result, if the elements of a vector must be processed sequentially, when a second element, stored in a smaller register, is ready for processing by an element processor, the processing of the second element need not wait the completion of the processing of a first element stored in the same vector register.

公开(公告)号：DE3750520T2

公开(公告)日：1995-04-06

申请号：DE3750520

申请日：1987-04-14

Applicant: IBM

Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

IPC: G06F9/22 ,  G06F15/16 ,  G06F17/16

Abstract: A method for optimizing performance in a fixed clock rate computer system. A control word is provided having a control portion for operational instructions and a programmable timing portion. The programmable timing portion includes a value representative of the sum of execution time and inter-execution delay time. A counter (22i) is provided for receiving the value representative of the execution and inter-execution times. The counter is capable of generating a signal (EOS) to indicate an end of decrementing operation. The operational instructions are executed simultaneously with the processing of the time value in the counter so that a subsequent instruction is executed only when an end of operation signal is received from the counter.

公开(公告)号：DE3686828T2

公开(公告)日：1993-04-01

申请号：DE3686828

申请日：1986-02-14

Applicant: IBM

Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

IPC: G06F17/16 ,  G06F15/80 ,  G06F15/347 ,  G06F15/76

Abstract: A parallel vector processor includes a plurality of vector registers, each vector register being subdivided into a plurality of smaller registers. A vector is stored in each vector register, the vector has a plurality of elements. The elements of the vector are assigned for storage in the smaller registers of the vector register. In the parallel vector processor, assume that each vector register is subdivided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers. The second and third successive M elements of the N element vector are each processed by the element processors 1 through M. As a result, if the elements of a vector must be processed sequentially, when a second element, stored in a smaller register, is ready for processing by an element processor, the processing of the second element need not wait the completion of the processing of a first element stored in the same vector register.