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    PHOTOLITHOGRAPHIC CRITICAL DIMENSION CONTROL USING RETICLE MEASUREMENTS
    1.
    发明公开
    PHOTOLITHOGRAPHIC CRITICAL DIMENSION CONTROL USING RETICLE MEASUREMENTS 有权
    临界尺寸光刻控制中的应用RETIKELMESSUNGEN

    公开(公告)号：EP1470447A4

    公开(公告)日：2007-10-10

    申请号：EP02784585

    申请日：2002-11-25

    Applicant: IBM

    Inventor： RANKIN JED H ,  SCHNEIDER CRAIN E ,  SMYTH JOHN S ,  WATTS ANDREW J

    IPC: G03C5/00 ,  G01D18/00 ,  G03F7/20 ,  G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  H01L21/027

    CPC classification number: G03F7/70508 ,  G03F7/70558

    Abstract: A method of implementing a new reticle for manufacturing semiconductor devices on a wafer which involves performing measurements (420) on the reticle and assigning an initial exposure dose (470) by using a predetermined algorithm (450). The exposure control system (490) utilizes reticle CD data (430, 440) for automatically calculating reticle exposure offset values, i.e. reticle factors (510). A correlation of reticle size deviations (500) to calculated reticle factors (510) is used to derive a reticle factor (510) for the new reticle. The derived reticle factor (510) is then used to predict (450) an initial exposure condition for the new reticle which is applied (470) to the lithography tool (410) for achieving a wafer design dimension.

    STRUCTURE AND METHODOLOGY FOR FABRICATION AND INSPECTION OF PHOTOMASKS
    3.
    发明申请
    STRUCTURE AND METHODOLOGY FOR FABRICATION AND INSPECTION OF PHOTOMASKS 审中-公开
    光电子制造和检验的结构与方法

    公开(公告)号：WO2006121903A2

    公开(公告)日：2006-11-16

    申请号：PCT/US2006017491

    申请日：2006-05-05

    Applicant: IBM ,  RANKIN JED H ,  WATTS ANDREW J

    Inventor： RANKIN JED H ,  WATTS ANDREW J

    IPC: G06F17/50

    CPC classification number: G03F1/84

    Abstract: A photomask (100), method of designing, of fabricating, of designing, a method of inspecting and a system for designing the photomask (100). The photomask (100), includes: a cell region (110), the cell region (110) comprising one or more chip regions (155 A, 155B, 155C, 155D), each chip region (155 A, 155B, 155C, 155D) comprising a pattern of opaque and clear sub-regions corresponding to features of an integrated circuit chip and one or more kerf regions (160A, 160B, 160C, 160D), each kerf region (160A, 160B, 160C, 160D) comprising a pattern of opaque and clear sub-regions corresponding to features of an integrated circuit kerf; a clear region (125A) formed adjacent to a side of a copy region (170A, 170B), the copy region (170A, 170B) comprising opaque and clear sub-regions that are copies of at least a part of the cell region (110); and an opaque region (115) between the clear region (125A, 125B, 125C, 125D) and the cell region (110).

    Abstract translation: 光掩模（100），设计方法，设计方法，检测方法以及设计光掩模（100）的系统。 光掩模（100）包括：单元区域（110），单元区域（110）包括一个或多个芯片区域（155A，155B，155C，155D），每个芯片区域（155A，155B，155C，155D ）包括对应于集成电路芯片和一个或多个切口区域（160A，160B，160C，160D）的特征的不透明和透明子区域的图案，每个切口区域（160A，160B，160C，160D）包括图案 对应于集成电路切口的特征的不透明和清晰的子区域; 形成在复制区域（170A，170B）的一侧附近的清晰区域（125A），所述复制区域（170A，170B）包括作为所述单元区域（110A）的至少一部分的复制品的不透明和清晰的子区域 ）; 以及在所述透明区域（125A，125B，125C，125D）和所述单元区域（110）之间的不透明区域（115）。

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