公开(公告)号：US3593317A

公开(公告)日：1971-07-13

申请号：US3593317D

申请日：1969-12-30

Applicant: IBM

Inventor： FLEISHER HAROLD ,  WEINBERGER ARNOLD ,  WINKLER VAUGHN D

IPC: H03K19/177 ,  G06C15/00

CPC classification number: H03K19/177

Abstract: An improved method and means to implement a logic function F of N variables by partitioning the logic operation in a plurality of generalized logic matrices. It is first mathematically demonstrated that a function F of N variables may be expanded into subfunctions of a lesser number of variables. These subfunctions may be logically implemented individually and then logically combined so as to produce the desired function of N variables with a concomitant savings in logic circuitry over that required if the functions were directly implemented. The means used to implement the logic function F are a plurality of generalized logic matrices, each of which comprises a plurality of logic gates arranged in columns and rows, an input decoder for accepting the input variables, and a storage register for varying the functions generated at the output of the matrix. These matrices are arranged in cascade so that, as the function F is constructed from the several subfunctions, additional variables are inserted at each matrix stage until the function F of N variables is fully generated.

公开(公告)号：US3623016A

公开(公告)日：1971-11-23

申请号：US3623016D

申请日：1969-09-29

Applicant: IBM

Inventor： WINKLER VAUGHN D

IPC: G06F3/023 ,  G06K1/06 ,  H03K17/972 ,  H03M11/22 ,  H04L13/16 ,  G08B29/00 ,  H04L3/00

CPC classification number: H03K17/972 ,  G06F3/023

Abstract: Keyboard providing character coded information with each key depression is described. Information storage apparatus is included within the keyboard for storing one or more discrete character codes. By suitably controlling the access to the stored information, a plurality of multicharacter messages may be obtained with each key depression. The memory may be of the readwrite type permitting security control of the data transmitted between the keyboard of a terminal and the central processing unit of a computer. Provision is included in each key for providing an electronic interlock to permit operation in a burst mode.

公开(公告)号：US3202969A

公开(公告)日：1965-08-24

申请号：US86296759

申请日：1959-12-30

Applicant: IBM

Inventor： DUNWELL STEPHEN W ,  ERNEST STEPHENS CLARENCE ,  STRINGFELLOW WILLIAM R ,  WINKLER VAUGHN D

IPC: G06F9/38 ,  G06F15/16

CPC classification number: G06F9/3867 ,  G06F15/16

公开(公告)号：CA769310A

公开(公告)日：1967-10-10

申请号：CA769310D

Applicant: IBM

Inventor： DUNWELL STEPHEN W ,  STRINGFELLOW WILLIAM R ,  STEPHENS CLARENCE E ,  WINKLER VAUGHN D

公开(公告)号：FR2276738A1

公开(公告)日：1976-01-23

申请号：FR7515093

申请日：1975-05-06

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HILLER RICHARD ,  OTTAWAY GERALD H ,  WINKLER VAUGHN D

IPC: G06F7/48 ,  G06K9/46 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20 ,  G06K9/00 ,  G11C19/14

Abstract: 1476880 Character recognition programmable logic circuit INTERNATIONAL BUSINESS MACHINES CORP 17 April 1975 [24 June 1974 (2)] 15770/75 Heading G4R A logic circuit arrangement for use in a character recognition device has a shift register SR1- 48 feeding a plurality of programmable logic circuits P AND 1-48. Data representing for instance a scanning matric 40 Î 24 is fed serially to a 960 bit shift register formed of 48 20 bit sections. Each section feeds a plurality of programmable AND circuits 1-48 each of which produces a one bit output which is fed back to 64 feedback latches which also feed the P AND circuits. Selected P AND circuits 37-48 also feed output latches. The P AND circuits may be as shown in Fig. 8C for a three input gate in which latches 115, 116, 124, 125, 133, 134 are set to determine the logic operation. If both latches for an input are zero the inverters, e.g. 119, 120 for input A feed "1"s to AND gate 123. If only one is zero then either A or A is fed to gate 123. OR functions are produced using inverters and de Morgan's theorem A - B = A + B. The shift register may contain dummy registers which are not connected to the logic circuits to reduce the number of connections required while still storing the same number of bits. Thus portions of an area are processed alternately (Fig. 14, not shown).

公开(公告)号：CA1053803A

公开(公告)日：1979-05-01

申请号：CA225122

申请日：1975-04-17

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  OTTAWAY GERALD H ,  WINKLER VAUGHN D

IPC: G06K9/46 ,  H03K19/177 ,  G06K9/06 ,  H03K19/08

Abstract: Improved features for a fabrication arrangement that reduces the number of LSI chips required in a bit stream measurement system comprised of a plurality of measurement elements, each element including a large programmable array. The improvements relate the chip and measurement element fabrication to the detection significance of parts of the bit stream by substituting delay shift registers for array portions to handle the less significant parts of the bit stream in some measurement elements. The detection operations can then be concentrated on the more significant parts of a bit stream, such as the part representing the top, bottom, left or right portion of an optical character recognition machines bit stream represented character frame. The resulting modifications in chip and element fabrication result in a further reduction in the average number of chips required in the measurement system. The LSI array chips can be identically made.