公开(公告)号：CA1171471A

公开(公告)日：1984-07-24

申请号：CA372655

申请日：1981-03-10

Applicant: IBM

Inventor： BERNDLMAIER ERICH ,  DORLER JACK A ,  MOSLEY JOSEPH M ,  WEITZEL STEPHEN D

IPC: H03K19/00 ,  G05F1/46 ,  G06F1/04 ,  G06F1/10 ,  H03K3/03 ,  H03K5/00 ,  H03K19/0175 ,  H03K19/086 ,  H03L7/089 ,  H03L7/099

Abstract: POWER CONTROL MEANS FOR ELIMINATING CIRCUIT TO CIRCUIT DELAY DIFFERENCES AND PROVIDING A DESIRED CIRCUIT DELAY An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. is described. The on chip delay regulator compares a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. In an example a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock). FI9-80-020

公开(公告)号：CA1278349C

公开(公告)日：1990-12-27

申请号：CA561205

申请日：1988-03-11

Applicant: IBM

Inventor： MALEY GERALD A ,  MOSLEY JOSEPH M ,  WEITZEL STEPHEN D

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/007

Abstract: FAULT TOLERANT LOGICAL CIRCUITRY A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one of the first and second interconnected signal paths.