公开(公告)号：US3928857A

公开(公告)日：1975-12-23

申请号：US39290073

申请日：1973-08-30

Applicant: IBM

Inventor： CARTER RICHARD S ,  HOGAN JR SPURGEON G ,  LEUNG WAN L ,  MCGILVRAY BRUCE L ,  WERNER ROBERT H

IPC: G06F9/38 ,  G06F9/06

CPC classification number: G06F9/381

Abstract: Apparatus for fetching instructions to an instruction register of a central processing unit, including instruction buffers for storing instructions prior to their execution in the CPU (lookahead) and apparatus for storing instructions which have been executed in the CPU (look-behind) in anticipation of their further use in, for example, programming loops. The look-behind apparatus comprises a multi-word buffer with its associated data register. The buffer data register, in addition to its function as part of the look-behind apparatus, also provides an additional level of look-ahead.

Abstract translation: 用于将指令读取到中央处理单元的指令寄存器的装置，包括用于在执行CPU之前存储指令的指令缓冲器（先行）以及用于存储在CPU（后视）中执行的指令的装置 预期他们在例如编程循环中进一步使用它们。 该查看装置包括具有相关联的数据寄存器的多字缓冲器。 缓冲器数据寄存器除了作为俯视设备的一部分的功能之外，还提供了一个额外的预览级别。

公开(公告)号：CA1017871A

公开(公告)日：1977-09-20

申请号：CA206893

申请日：1974-08-13

Applicant: IBM

Inventor： CARTER RICHARD S ,  HOGAN SPURGEON G JR ,  LEUNG WAN L ,  MCGILVRAY BRUCE L ,  WERNER ROBERT H

IPC: G06F9/38

Abstract: Apparatus for fetching instructions to an instruction register of a central processing unit, including instruction buffers for storing instructions prior to their execution in the CPU (look-ahead) and apparatus for storing instructions which have been executed in the CPU (look-behind) in anticipation of their further use in, for example, programming loops. The look-behind apparatus comprises a multi-word buffer with its associated data register. The buffer data register, in addition to its function as part of the look-behind apparatus, also provides an additional level of look-ahead.

公开(公告)号：CA1143852A

公开(公告)日：1983-03-29

申请号：CA360340

申请日：1980-09-16

Applicant: IBM

Inventor： CHRISTENSEN NEAL T ,  VAN LOO WILLIAM C ,  WERNER ROBERT H ,  WETZEL JOSEPH A ,  ZEITLER CARL JR

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16 ,  G06F15/177

Abstract: MULTIPROCESSOR MECHANISM FOR HANDLING CHANNEL INTERRUPTS The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program. An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty. A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs. In each CP, acceptance determining circuits connect to the broadcast bus and accept the highest-priority-unmask nonempty-state bit position being broadcast. From this, the CP sends the SC an accepted queue identifier signal and an accept signal when the CP is in an interruptable state. The CP also sends to the SC a wait state signal if the CP is then in wait state. Selection determining circuits in the SC receive the accept, wait (if any), and queue identifier signals from all accepting CPs and select one accepting CP per accepted queu at any one time. The selection circuits can perform the selection of plural CPs in parallel, and send a select signal to each selected CP. An inhibit register in the interrupt controller in the SC inhibits selected bits on the broadcast bus to all CPs except the selected CP for the selected queue identifier. The inhibit on any bit is removed when the selected CP ends it acceptance of the P09-79-011 corresponding queue, so that any CP can select the next entry on the corresponding queue. When any selected CP finds it has emptied a queue, it activates a reset line to the SC which resets the corresponding bit in the pending register to indicate the empty state. PO9-79-011