公开(公告)号：JP2005149492A

公开(公告)日：2005-06-09

申请号：JP2004314811

申请日：2004-10-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SANDON PETER A ,  WEST R MICHAEL P

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F9/34 ,  G06F15/00 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16

CPC classification number: G06F9/3012 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30145 ,  G06F15/8084

Abstract: PROBLEM TO BE SOLVED: To provide a processor and a method for processing matrix data. SOLUTION: The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N>2, M>2, K>1 and B>1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays so that the operation is performed with selectivity with respect to the data elements of the first array. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于处理矩阵数据的处理器和方法。 解决方案：处理器包括M个独立的向量寄存器文件，其适于集中存储L个数据元素的矩阵。 每个数据元素都有B位二进制位。 矩阵具有N行和M列，L = N * M。 每列有K个子列。 N> 2，M> 2，K> 1和B> 1。 每行和每个子列都是可寻址的。 处理器不会重复存储L个数据元素。 矩阵包括一组阵列，使得每个数组是矩阵的行或子列。 处理器可以执行对该组阵列的第一阵列执行操作的指令，使得相对于第一阵列的数据元素的选择性执行操作。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：DE69126962D1

公开(公告)日：1997-09-04

申请号：DE69126962

申请日：1991-05-16

Applicant: IBM

Inventor： BUTLER NICHOLAS DAVID ,  WEST R MICHAEL P

IPC: G06F12/06 ,  G06F12/04 ,  G09G5/00 ,  G09G5/36 ,  G09G5/395 ,  G11C7/10 ,  G09G1/16 ,  G11C7/00

Abstract: A common requirement for a display adapter for multimedia applications is to be able to support two display "layers" simultaneously accessed from display memory. For each displayed pixel the two display layers are merged with various forms of mixing possible. The obvious way of displaying these two layers is to hold each layer in separate VRAMs and use the VRAM serial ports to access the two layers simultaneously. However, with the low resolution displays and small memory sizes required for personal computers it is not possible to keep the two layers in separate VRAMs, and so both data streams must be fetched from a single VRAM, or bank of VRAMs. With conventional VRAMs this cannot be efficiently achieved. By a novel enhancement to a conventional "Split Shift Register" VRAM, the disclosed invention allows both layers to be accessed simply and efficiently from the same memory device(s). The disclosed invention finds application in the field of semiconductor memory devices, in particular VRAMs and other similar memory devices. The disclosed use of memory devices according to the invention finds application in the field of, but not limited to, display memory subsystems.

公开(公告)号：PH30720A

公开(公告)日：1997-10-02

申请号：PH49619

申请日：1994-12-19

Applicant: IBM

Inventor： RACKLEY DARWIN P ,  WEST R MICHAEL P

IPC: G09G5/06 ,  G09G5/02 ,  G09G5/08 ,  G09G5/38 ,  G06T11/00

Abstract: Apparatus is provided for adjusting the color of the sprite in display systems, so that the sprite is always distinctively visible irrespective of the underlying displayed data. A palette DAC 322 of a display system is provided with sprite control logic, which determines the color of a sprite to be overlaid on an image displayed on a video display unit 236 of a display system by inverting only the most significant bit (MSB) of each of the red, green and blue pixel data components of the underlying image. In a preferred embodiment, the sprite control logic circuit comprises first, second and third multiplexors (MUXes) 420, 422, 424 each having a first input connected to receive the MSB of the red, green and blue pixel data components of the underlying image, respectively, and a second input connected to receive the output of first, second and third XOR gates, respectively. Each of the first, second and third XOR gates similarly have a first input connected to receive the MSB of the red, green and blue pixel data components of the underlying image, respectively, and a second input connected to receive sprite data from a sprite RAM 324, which sprite data represents a sprite character to be overlaid on the displayed image.