公开(公告)号：CA2303726C

公开(公告)日：2005-01-11

申请号：CA2303726

申请日：2000-04-05

Applicant: IBM

Inventor： WHITLEY LAWRENCE D ,  NEAL DANNY M ,  YANES ADALBERTO G ,  KELLY RICHARD A

IPC: G06F13/10 ,  G06F3/00 ,  G06F13/00 ,  G06F13/14 ,  G06F13/20 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40

Abstract: Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transactio n involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size isgreater than the available free block and greater than th e available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.

公开(公告)号：CA2303726A1

公开(公告)日：2000-11-18

申请号：CA2303726

申请日：2000-04-05

Applicant: IBM

Inventor： KELLY RICHARD A ,  NEAL DANNY M ,  WHITLEY LAWRENCE D ,  YANES ADALBERTO G

IPC: G06F13/10 ,  G06F3/00 ,  G06F13/00 ,  G06F13/14 ,  G06F13/20 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40

Abstract: Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transaction involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size is greater than the available free block and greater than the available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.

公开(公告)号：CA1201534A

公开(公告)日：1986-03-04

申请号：CA440691

申请日：1983-11-08

Applicant: IBM

Inventor： WHITLEY LAWRENCE D

IPC: G06F9/318 ,  G06F9/35 ,  G06F9/355 ,  G06F12/10

Abstract: INDEXED-INDIRECT ADDRESSING USING PREFIX CODES The present invention provides multi-level indexed indirection for all instructions in the instruction set of a data processor, without any architectural penalty except the use of a single op-code point per operand in the instruction. That is, a one-address machine requires only one op-code point to provide indexed indirection for its entire instruction set; a two-address architecture requires a total of only two code points, and so forth.