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公开(公告)号：JPH10214142A
公开(公告)日：1998-08-11
申请号：JP32994397
申请日：1997-12-01
Applicant: IBM
Inventor： NEAL DANNY M , KELLEY RICHARD A
Abstract: PROBLEM TO BE SOLVED: To provide a PCI local bus architecture for supporting a high speed operation by using a 5V signal environment and a 5V PCI connector in a system having backward interchangeability with present architecture definition. SOLUTION: A PCI local bus 202 in a data processing system is operated with 50MHz by using a 5V environment having a 5V connector for an add-in board and a proper timing budget. Only a 5V add-in board can be used for a 50MHz adapter mounted on the bus. This bus has backward interchangeability with existing 33MHz PCI specification, and when a 33MHz adapter is mounted, this is operated with 33MHz, and when a 50MHz adapter or a 66MHz adapter using a general board or both are mounted, this is operated with 50MH.
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公开(公告)号：JPH10187594A
公开(公告)日：1998-07-21
申请号：JP32661097
申请日：1997-11-27
Applicant: IBM
Inventor： NEAL DANNY M , THURBER STEVEN M
Abstract: PROBLEM TO BE SOLVED: To provide a method for supporting equal access between different peripheral component mutual connections (PCI) inside a data processing system. SOLUTION: In the case of access request from a PCI device, 1st discrimination is performed concerning whether the access request is outputted to a system memory 15 connected to a system bus 28 or not. In response to discrimination showing that the access request is not outputted to the system memory 15 connected to the system bus 28, the other discrimination is performed concerning whether the access request is outputted to a PCI device belonging to the same PCI host/bridge 11 as the request side PCI device or not. In response to the discrimination showing that the access request is not outputted to the PCI device belonging to the same PCI host bridge as the request side PCI device, an additional protocol is executed for supporting the PCI equal access request between the different PCI host bridges inside the data processing system.
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公开(公告)号：MX146052A
公开(公告)日：1982-05-06
申请号：MX17763979
申请日：1979-05-14
Applicant: IBM
Inventor： BOWLES DAVID J , JOHNSON CARL F , CLANCY DOUGLAS E , NEAL DANNY M
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公开(公告)号：CA1103602A
公开(公告)日：1981-06-23
申请号：CA322251
申请日：1979-02-22
Applicant: IBM
Inventor： BOWLES DAVID J , CLANCY DOUGLAS E , JOHNSON CARL F , NEAL DANNY M
Abstract: RELOCATE FEATURE FOR AN ELECTRONIC TYPEWRITER of the Invention On electronic typewriters which have the ability to record into a small working memory those characters, functions and escapements which are keyed at the keyboard, it is many times advantageous to be able to place the carrier and the print point over a character which has been previously typed without using repeated backspaces. Disclosed herein is a feature for an electronic typewriter which permits the operator to easily align the print point with a character on the page by positioning a reference mark on the card holder or print carrier in relation to a previously printed character and then through keyboard control cause the carriage to shift its position such that the print point is then exactly aligned with the character printed. The positioning of the carrier such that the reference mark is in relation to the desired print point is accomplished by a backspace operation and the repositioning or causing of the carrier to assume a position immediately over the subject character is accomplished by keyboard control through the electronics of the typewriter to cause the carrier to shift a predetermined distance. LE9-78-006
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公开(公告)号：CA2273719C
公开(公告)日：2004-03-30
申请号：CA2273719
申请日：1999-06-04
Applicant: IBM
Inventor： FUHS RONALD E , BEUKEMA BRUCE L , THURBER STEVEN MARK , NEAL DANNY M , KELLEY RICHARD A
Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 1 00 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking da ta on only one clock edge, or by clocking data on both a rising edge and a falling edge of a cloc k signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions o r alias split transactions to delayed transactions. Backward compatibility may also be provided for option al features such as hot-pluggability.
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Patent Agency Ranking
公开(公告)号：CA2273719A1
公开(公告)日：2000-01-15
申请号：CA2273719
申请日：1999-06-04
Applicant: IBM
Inventor： BEUKEMA BRUCE L , THURBER STEVEN MARK , NEAL DANNY M , FUHS RONALD E , KELLEY RICHARD A
Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.
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公开(公告)号：FR2426572A1
公开(公告)日：1979-12-21
申请号：FR7910425
申请日：1979-04-17
Applicant: IBM
Inventor： CLANCY DOUGLAS E , JOHNSON CARL F , MCCRAY WILLIAM R , NEAL DANNY M
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公开(公告)号：CA2303726C
公开(公告)日：2005-01-11
申请号：CA2303726
申请日：2000-04-05
Applicant: IBM
Inventor： WHITLEY LAWRENCE D , NEAL DANNY M , YANES ADALBERTO G , KELLY RICHARD A
Abstract: Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transactio n involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size isgreater than the available free block and greater than th e available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.
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公开(公告)号：CA2303726A1
公开(公告)日：2000-11-18
申请号：CA2303726
申请日：2000-04-05
Applicant: IBM
Inventor： KELLY RICHARD A , NEAL DANNY M , WHITLEY LAWRENCE D , YANES ADALBERTO G
Abstract: Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transaction involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size is greater than the available free block and greater than the available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.
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公开(公告)号：FR2426575A1
公开(公告)日：1979-12-21
申请号：FR7910426
申请日：1979-04-17
Applicant: IBM
Inventor： BOWLES DAVID J , CLANCY DOUGLAS E , JONHSON CARL F , NEAL DANNY M
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