公开(公告)号：JPH10283178A

公开(公告)日：1998-10-23

申请号：JP4930398

申请日：1998-03-02

Applicant: IBM

Inventor： GETZLAFF KLAUS JOERG ,  LEPPLA BERND ,  PFEFFER ERWIN ,  PFLUEGER THOMAS ,  WITHELM BIRGIT

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To issue an instruction to an execution unit even at the time of a continuous sequence and back-to-back in a random processing system by setting the valid bit of the target operand before the target operand of the instruction becomes usable. SOLUTION: The instruction is taken out from an instruction memory 100 and successively buffered in an instruction cache 101, then the instruction is decoded to a common internal instruction format and then, the instruction is transferred to a reservation station 103. In the reservation station 103, the instruction stands by until issuance to one of function units can be performed. In such a random processing system, the valid bit of the target operand is set before the target operand of the instruction becomes usable. A source operand is generated as the target operand of a preceding instruction and the instruction is immediately issued when the valid bit is set to the entire source operands.

公开(公告)号：DE19804146A1

公开(公告)日：1998-09-17

申请号：DE19804146

申请日：1998-02-03

Applicant: IBM

Inventor： GETZLAFF KLAUS DIPL ING ,  LEPPLA BERND DIPL ING ,  PFEFFER ERWIN DIPL ING ,  PFLUEGER THOMAS DIPL ING ,  WITHELM BIRGIT

IPC: G06F9/38

Abstract: The system has at least one command supply unit. A command buffer stores commands and specifies the source operand and the target operand of the commands. An operand is specified as a target operand of a first command in the buffer and as a source operand of a second command in the buffer. The system has an output device to output the commands to one of the command supply units. The output device outputs a command when all source operands of the command are sufficient. The system also has a display device to show the source operands of the second command as sufficient after the first command is output to a first command supply unit and before the value of the operands is provided.

公开(公告)号：DE4307139A1

公开(公告)日：1994-09-08

申请号：DE4307139

申请日：1993-03-06

Applicant: IBM

Inventor： FISCHER WOLFGANG DIPL ING ,  GETZLAFF KLAUS JOERG DIPL ING ,  KURZ BRIGITTE ,  TAST HANS-WERNER DIPL ING ,  WILLE UDO DIPL ING ,  WITHELM BIRGIT

IPC: G06F13/362 ,  G06F15/17 ,  G06F13/36

Abstract: A method of making processors (PU0 to Pn) of a multiprocessor system (MP) quiescent, or of serialising bus assignments for the individual processors, is described. This serialisation becomes necessary if one or more processors simultaneously want to execute commands which require uninterrupted ownership of the bus for as long as they are being executed, e.g. to prevent damage to the integrity of data. For this purpose, a quiescent-making network (QN), which connects all processors, is used. Processors which execute such atomic commands receive their bus assignment on a priority basis. The processor with the highest rank puts its competitors into conditional branch command loops (BC loops), in which they wait for a specified condition, e.g. "QN not blocked" (QU+). If this condition is fulfilled, e.g. after the end of an atomic command, the processor with the next lower priority receives the bus. Processors which are executing other commands are forced into a no-operation state (NOP), from which they are released after completion of the atomic command of another processor, to resume their interrupted commands.

公开(公告)号：DE19614481A1

公开(公告)日：1997-10-16

申请号：DE19614481

申请日：1996-04-12

Applicant: IBM

Inventor： WILLE UDO ,  GETZLAFF KLAUS-JOERG ,  WITHELM BIRGIT ,  TAST HANS-WERNER

IPC: G06F12/0897 ,  G06F12/08 ,  G06F13/16 ,  G06F15/16

Abstract: The second order cache memory (L2) has a directory (9) which stores an address i and validity bit Vi(L1) for each of its memory sectors Yi. The value of each validity bit depends on whether the contents of sector Yi are also stored in the corresponding sector Zj of a first order cache memory (L1). Both cache memories store the V-, MC- and C-bits used for MESI cache protocol.

公开(公告)号：DE4307139C2

公开(公告)日：1997-02-13

申请号：DE4307139

申请日：1993-03-06

Applicant: IBM

Inventor： FISCHER WOLFGANG DIPL ING ,  GETZLAFF KLAUS JOERG DIPL ING ,  KURZ BRIGITTE ,  TAST HANS-WERNER DIPL ING ,  WILLE UDO DIPL ING ,  WITHELM BIRGIT

IPC: G06F13/362 ,  G06F15/17 ,  G06F13/364 ,  G06F9/46