公开(公告)号：JPH10315122A

公开(公告)日：1998-12-02

申请号：JP10926798

申请日：1998-04-20

Applicant: IBM

Inventor： WILLIAM FRANCIS LANDERS ,  MICHAEL FRANCES LOFARO ,  ADAM DAN CHICKNER

IPC: B24B1/04 ,  B24B37/10 ,  B24B37/22 ,  H01L21/304 ,  B24B37/04 ,  B24B37/00

Abstract: PROBLEM TO BE SOLVED: To prevent a particle from depositing on a chemical machinery polishing pad used for chemical-machinery-like polishing by successively laminating a platen mutually connecting layer formed on a platen, an active layer having a vibration module incorporated into it and an energy transport layer opposed to the pad. SOLUTION: As a method to form a device to prevent a particle from depositing on a polishing pad 70, a platen mutually connecting layer 120 mutually connected to a platen 55 of a chemical-machinery-like polishing device 50 is formed, and an active layer 130 is formed on its mutually connecting layer 120, and an energy transport layer 140 is formed on the active layer 130 opposed to the pad 70. When an active layer is formed, the active layer 130 to selectively vibrate an area of the energy transport layer 140 is formed, and when an energy transport layer is formed, the energy transport layer 140 to selectively transmit vibration to the polishing pad 70 arranged on the energy transport layer 140 is formed.

公开(公告)号：GB2583864B

公开(公告)日：2022-07-13

申请号：GB202011413

申请日：2019-01-14

Applicant: IBM

Inventor： JOSHUA THOMAS SMITH ,  KEVIN WINSTEL ,  WILLIAM FRANCIS LANDERS ,  TERESA JACQUELINE WU

IPC: H01L21/768 ,  B01D15/34 ,  G01N30/60

Abstract: Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.

公开(公告)号：GB2583864A

公开(公告)日：2020-11-11

申请号：GB202011413

申请日：2019-01-14

Applicant: IBM

Inventor： JOSHUA THOMAS SMITH ,  KEVIN WINSTEL ,  WILLIAM FRANCIS LANDERS ,  TERESA JACQUELINE WU

IPC: H01L21/768

Abstract: Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.