公开(公告)号：JP2008010876A

公开(公告)日：2008-01-17

申请号：JP2007168478

申请日：2007-06-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  BOOTH ROGER ALLEN JR ,  WILLIAM PAUL HOVIS

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a fin FET structure and its manufacturing method.
SOLUTION: The manufacturing method includes the steps for forming a silicon fin on the top surface of a bulk silicon substrate, forming gate dielectrics on the sidewalls at both sides of the fin, forming a gate electrode which comes into contact directly and physically with the gate dielectric layer on the sidewalls at both sides of the fin, forming a primary source/drain at a primary side fin in the channel region and forming a secondary source/drain at a secondary side fin in the channel region, removing a part of the bulk silicon substrate from the underside of at least one part of the primary and secondary source/drain regions for creating the void, and filling the void with the dielectric materials. The structure includes a body contact between a silicon body of the fin FET and the bulk silicon substrate.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供鳍式FET结构及其制造方法。 解决方案：制造方法包括在体硅衬底的顶表面上形成硅翅片的步骤，在翅片两侧的侧壁上形成栅极电介质，形成直接和物理接触的栅电极 在鳍的两侧的侧壁上具有栅介质层，在沟道区中的初级侧鳍形成初级源极/漏极，并在沟道区中的次级侧鳍形成次级源极/漏极，去除部分 从主源极/漏极区的至少一部分的下侧开始的体硅衬底产生空隙，并用电介质材料填充空隙。 该结构包括鳍状FET的硅体和体硅衬底之间的体接触。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2013123077A

公开(公告)日：2013-06-20

申请号：JP2013025314

申请日：2013-02-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： MANDELMAN JACK ALLAN ,  ROGER ALLEN BOOTH JR ,  WILLIAM PAUL HOVIS

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a finFET structure and a method of fabricating the same.SOLUTION: The method includes: forming a silicon fin on a top surface of a bulk silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of a channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the bulk silicon substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the bulk silicon substrate.

Abstract translation: 要解决的问题：提供finFET结构及其制造方法。 解决方案：该方法包括：在体硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 形成与所述鳍片的相对侧壁上的栅极电介质层直接物理接触的栅电极; 在通道区域的第一侧上在所述鳍片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除体硅衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和体硅衬底之间的体接触。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：MY105290A

公开(公告)日：1994-09-30

申请号：MYPI19910126

申请日：1991-01-25

Applicant: IBM

Inventor： JAMES ANDREW YANKOSKY ,  WILLIAM PAUL HOVIS ,  CHARLES EDWARD DRAKE ,  SCOTT CLARENCE LEWIS ,  DANIEL JOHN NICKEL ,  CHARLES HENRI STAPPER ,  JOHN ATKINSON FITFIELD ,  HOWARD LEO KALTER ,  JOHN EDWARD BARTH JR

IPC: G06F11/10 ,  G06F11/20 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

Abstract: A DRAM HAVING ON-CHIP ECC AND BOTH BIT AND WORD REDUNDANCY THAT HAVE BEEN OPTIMIZED TO SUPPORT THE ON-CHIP ECC. THE BIT LINE REDUNDANCY FEATURES A SWITCHING NETWORK THAT PROVIDES AN ANY-FOR-ANY SUBSTITUTION FOR THE BIT LINES IN THE ASSOCIATED MEMORY ARRAY. THE WORD LINE REDUNDANCY IS PROVIDED IN A SEPARATE ARRAY SECTION, AND HAS BEEN OPTIMIZED TO MAXIMIZE SIGNAL WHILE REDUCING SOFT ERRORS. THE ARRAY STRORES DATA IN THE FORM OF ERROR CORRECTION WORDS (ECWS) ON EACH WORD LINE. A FIRST SET OF DATA LINES (FORMED IN A ZIG-ZAG PATTERN TO MINIMIZE UNEQUAL CAPACITIVE LOADING ON THE UNDERLYING BIT LINES) ARE COUPLED TO READ OUT AN ECW AS WELL AS THE REDUNDANT BIT LINES. A SECOND SET OF DATA LINES RECEIVE THE ECW AS CORRECTED BY BIT LINE REDUNDANCY, AND A THIRD SET OF DATA LINES RECEIVE THE ECW AS CORRECTED BY THE WORD LINE REDUNDANCY. THE THIRD SET OF DATA LINES ARE COUPLED TO THE ECC BLOCK, WHICH CORRECTS ERRORS ENCOUNTERED IN THE ECW. THE ECC CIRCUITRY IS OPTIMIZED TO REDUCE THE ACCESS DELAYS INTRODUCED BY CARRYING OUT ON-CHIP ERROR CORRECTION. THE ECC BLOCK PROVIDES BOTH THE CORRECTED DATA BITS AND THE CHECK BITS TO AN SRM. THUS, THE CHECK BITS CAN BE EXTERNALLY ACCESSED, IMPROVING TESTABILITY OF THE MEMORY CHIP. AT THE SAME TIME, HAVING A SET OF INTERRELATED BITS IN THE SRM IMPROVES ACCESS PERFORMANCE WHEN USING MULTI-BIT ACCESS MODES, WHICH COMPENSATES FOR WHATEVER ACCESS DELAYS ARE INTRODUCED BY THE ECC. TO MAXIMIZE THE EFFICIENCY OF SWITCHING FROM MODE TO MODE, THE MODES ARE SET AS A FUNCTION OF RECEIVED ADDRESS SIGNALS. (FIG. 5)