公开(公告)号：SG97224A1

公开(公告)日：2003-07-18

申请号：SG200107478

申请日：2001-11-26

Applicant: IBM

Inventor： DARREN L ANAND ,  JOHN EDWARD BARTH JR ,  JOHN ATKINSON FIFIELD ,  PAMELA SUE GILLIS ,  PETER O JAKOBSEN ,  DOUGLAS WAYNE KEMERER ,  DAVID E LACKEY ,  STEVEN FREDERICK OAKLAND ,  MICHAEL RICHARD QUELLETTE ,  WILLIAM ROBERT TONTI

IPC: H01L21/82 ,  G11C7/00 ,  G11C29/00 ,  G11C29/04 ,  H03K19/173 ,  H05K7/00

Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

公开(公告)号：MY105290A

公开(公告)日：1994-09-30

申请号：MYPI19910126

申请日：1991-01-25

Applicant: IBM

Inventor： JAMES ANDREW YANKOSKY ,  WILLIAM PAUL HOVIS ,  CHARLES EDWARD DRAKE ,  SCOTT CLARENCE LEWIS ,  DANIEL JOHN NICKEL ,  CHARLES HENRI STAPPER ,  JOHN ATKINSON FITFIELD ,  HOWARD LEO KALTER ,  JOHN EDWARD BARTH JR

IPC: G06F11/10 ,  G06F11/20 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

Abstract: A DRAM HAVING ON-CHIP ECC AND BOTH BIT AND WORD REDUNDANCY THAT HAVE BEEN OPTIMIZED TO SUPPORT THE ON-CHIP ECC. THE BIT LINE REDUNDANCY FEATURES A SWITCHING NETWORK THAT PROVIDES AN ANY-FOR-ANY SUBSTITUTION FOR THE BIT LINES IN THE ASSOCIATED MEMORY ARRAY. THE WORD LINE REDUNDANCY IS PROVIDED IN A SEPARATE ARRAY SECTION, AND HAS BEEN OPTIMIZED TO MAXIMIZE SIGNAL WHILE REDUCING SOFT ERRORS. THE ARRAY STRORES DATA IN THE FORM OF ERROR CORRECTION WORDS (ECWS) ON EACH WORD LINE. A FIRST SET OF DATA LINES (FORMED IN A ZIG-ZAG PATTERN TO MINIMIZE UNEQUAL CAPACITIVE LOADING ON THE UNDERLYING BIT LINES) ARE COUPLED TO READ OUT AN ECW AS WELL AS THE REDUNDANT BIT LINES. A SECOND SET OF DATA LINES RECEIVE THE ECW AS CORRECTED BY BIT LINE REDUNDANCY, AND A THIRD SET OF DATA LINES RECEIVE THE ECW AS CORRECTED BY THE WORD LINE REDUNDANCY. THE THIRD SET OF DATA LINES ARE COUPLED TO THE ECC BLOCK, WHICH CORRECTS ERRORS ENCOUNTERED IN THE ECW. THE ECC CIRCUITRY IS OPTIMIZED TO REDUCE THE ACCESS DELAYS INTRODUCED BY CARRYING OUT ON-CHIP ERROR CORRECTION. THE ECC BLOCK PROVIDES BOTH THE CORRECTED DATA BITS AND THE CHECK BITS TO AN SRM. THUS, THE CHECK BITS CAN BE EXTERNALLY ACCESSED, IMPROVING TESTABILITY OF THE MEMORY CHIP. AT THE SAME TIME, HAVING A SET OF INTERRELATED BITS IN THE SRM IMPROVES ACCESS PERFORMANCE WHEN USING MULTI-BIT ACCESS MODES, WHICH COMPENSATES FOR WHATEVER ACCESS DELAYS ARE INTRODUCED BY THE ECC. TO MAXIMIZE THE EFFICIENCY OF SWITCHING FROM MODE TO MODE, THE MODES ARE SET AS A FUNCTION OF RECEIVED ADDRESS SIGNALS. (FIG. 5)