公开(公告)号：DE2527911A1

公开(公告)日：1976-01-08

申请号：DE2527911

申请日：1975-06-23

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  HILLER RICHARD ,  OTTAWAY GERALD HOWARD ,  WINKLER VAUGHN DONALD

IPC: G06F7/48 ,  G06K9/46 ,  H03K19/173 ,  H03K19/177 ,  G06K9/06

Abstract: 1476880 Character recognition programmable logic circuit INTERNATIONAL BUSINESS MACHINES CORP 17 April 1975 [24 June 1974 (2)] 15770/75 Heading G4R A logic circuit arrangement for use in a character recognition device has a shift register SR1- 48 feeding a plurality of programmable logic circuits P AND 1-48. Data representing for instance a scanning matric 40 Î 24 is fed serially to a 960 bit shift register formed of 48 20 bit sections. Each section feeds a plurality of programmable AND circuits 1-48 each of which produces a one bit output which is fed back to 64 feedback latches which also feed the P AND circuits. Selected P AND circuits 37-48 also feed output latches. The P AND circuits may be as shown in Fig. 8C for a three input gate in which latches 115, 116, 124, 125, 133, 134 are set to determine the logic operation. If both latches for an input are zero the inverters, e.g. 119, 120 for input A feed "1"s to AND gate 123. If only one is zero then either A or A is fed to gate 123. OR functions are produced using inverters and de Morgan's theorem A - B = A + B. The shift register may contain dummy registers which are not connected to the logic circuits to reduce the number of connections required while still storing the same number of bits. Thus portions of an area are processed alternately (Fig. 14, not shown).

公开(公告)号：DE1178623B

公开(公告)日：1964-09-24

申请号：DEJ0019221

申请日：1960-12-24

Applicant: IBM

Inventor： DUNWELL STEPHEN W ,  STRINGFELLOW WILLIAM R ,  FALLS WAPPINGERS ,  WINKLER VAUGHN DONALD ,  STEPHENS CLARENCE ERNEST

IPC: G06F9/38 ,  G06F15/16

公开(公告)号：DE3473194D1

公开(公告)日：1988-09-08

申请号：DE3473194

申请日：1984-10-11

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  PANGERC DAVID M ,  WINKLER VAUGHN DONALD

IPC: H04N5/76 ,  B41J5/30 ,  G06F3/12 ,  G06F3/153 ,  G06K15/00 ,  G06K15/12 ,  G06T11/00

Abstract: An APA addressable printer (12) serves to generate a direct printed copy of the image vector-displayed on a storage tube (10) and the print-out of an arbitrarily predetermined information, respectively, or a combination of both. It provides both the image manipulation capability of an APA printer and the direct copying capability of an analog image copier in one device.