公开(公告)号：DE2527911A1

公开(公告)日：1976-01-08

申请号：DE2527911

申请日：1975-06-23

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  HILLER RICHARD ,  OTTAWAY GERALD HOWARD ,  WINKLER VAUGHN DONALD

IPC: G06F7/48 ,  G06K9/46 ,  H03K19/173 ,  H03K19/177 ,  G06K9/06

Abstract: 1476880 Character recognition programmable logic circuit INTERNATIONAL BUSINESS MACHINES CORP 17 April 1975 [24 June 1974 (2)] 15770/75 Heading G4R A logic circuit arrangement for use in a character recognition device has a shift register SR1- 48 feeding a plurality of programmable logic circuits P AND 1-48. Data representing for instance a scanning matric 40 Î 24 is fed serially to a 960 bit shift register formed of 48 20 bit sections. Each section feeds a plurality of programmable AND circuits 1-48 each of which produces a one bit output which is fed back to 64 feedback latches which also feed the P AND circuits. Selected P AND circuits 37-48 also feed output latches. The P AND circuits may be as shown in Fig. 8C for a three input gate in which latches 115, 116, 124, 125, 133, 134 are set to determine the logic operation. If both latches for an input are zero the inverters, e.g. 119, 120 for input A feed "1"s to AND gate 123. If only one is zero then either A or A is fed to gate 123. OR functions are produced using inverters and de Morgan's theorem A - B = A + B. The shift register may contain dummy registers which are not connected to the logic circuits to reduce the number of connections required while still storing the same number of bits. Thus portions of an area are processed alternately (Fig. 14, not shown).

公开(公告)号：CA1049145A

公开(公告)日：1979-02-20

申请号：CA225120

申请日：1975-04-17

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HILLER RICHARD

IPC: G06K9/03 ,  G06K9/46 ,  H03K19/177 ,  G06K9/06 ,  H03K19/08

Abstract: A fabrication arrangement using plural LSI chips to make a bit stream detection system requiring a programmable logic array which is too large to fit on a single LSI chip. Due to the small number of input/output pins available on any LSI chip, the fabrication arrangement divides among the chips an input shift register, the array, and array input latches. Each LSI chip also has time-multiplexed array outputs and time-multiplexed feedback inputs that minimize the pins and enable interconnection among the array section outputs on the chips so that they combine into the single large array required by the detection system. These LSI chips can be identically fabricated.

公开(公告)号：FR2276738A1

公开(公告)日：1976-01-23

申请号：FR7515093

申请日：1975-05-06

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HILLER RICHARD ,  OTTAWAY GERALD H ,  WINKLER VAUGHN D

IPC: G06F7/48 ,  G06K9/46 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20 ,  G06K9/00 ,  G11C19/14

Abstract: 1476880 Character recognition programmable logic circuit INTERNATIONAL BUSINESS MACHINES CORP 17 April 1975 [24 June 1974 (2)] 15770/75 Heading G4R A logic circuit arrangement for use in a character recognition device has a shift register SR1- 48 feeding a plurality of programmable logic circuits P AND 1-48. Data representing for instance a scanning matric 40 Î 24 is fed serially to a 960 bit shift register formed of 48 20 bit sections. Each section feeds a plurality of programmable AND circuits 1-48 each of which produces a one bit output which is fed back to 64 feedback latches which also feed the P AND circuits. Selected P AND circuits 37-48 also feed output latches. The P AND circuits may be as shown in Fig. 8C for a three input gate in which latches 115, 116, 124, 125, 133, 134 are set to determine the logic operation. If both latches for an input are zero the inverters, e.g. 119, 120 for input A feed "1"s to AND gate 123. If only one is zero then either A or A is fed to gate 123. OR functions are produced using inverters and de Morgan's theorem A - B = A + B. The shift register may contain dummy registers which are not connected to the logic circuits to reduce the number of connections required while still storing the same number of bits. Thus portions of an area are processed alternately (Fig. 14, not shown).