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    发明专利
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    公开(公告)号：DE1115488B

    公开(公告)日：1961-10-19

    申请号：DEJ0017527

    申请日：1960-01-14

    Applicant: IBM

    Inventor： WOLENSKY WILLIAM

    IPC: G06F12/04

    Abstract: 936,238. Electrical digital data storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 15, 1960 [Jan. 15, 1959], No. 1616/60. Class 106 (1). A register in a digital data storage apparatus is notionally divided into zones and data is extracted from the register in groups of bits (or bytes), means being provided for determining when adjacent bits of a byte are stored each in a different zone. When such a condition is sensed, data is registered in one zone simultaneously with further bytes being extracted from the other zone. In the embodiment described, data is stored in a main store in fixed length memory words of 64 bits and the bytes are of eight bits. Associated with the main store is a single memory word buffer register 72 connected to a 64-bit stream register 16 of the kind described in Specification 866,602 through a pair of gates, each of which pass half the buffer register to the stream register. Register 16 is divided into two zones by hypothetical boundaries after bits 31 and 63 and as soon as a byte extending across a boundary is extracted a new half word is entered into the zone in which its first bit lay. Four control registers are used in the extraction process: a word address register 30 in which is entered the address of the memory word in store containing the first bit of the required data; a byte size register 27 in which is stored the number of bits in the byte to be extracted; a bit address register 26 in which is stored the bit position of the first bit in the byte to be extracted; and a field length register in which is recorded the number of bits to be extracted. The process is performed in byte extraction cycles each controlled by X, Y and Z pulses produced by a clock, each pulse spanning an interval containing four read followed by four write times. An initial signal is applied to a flip-flop 1 raising the potential on. line 2 and thus activating one input of the AND units 10, 11 opening gate 68 to the contents of register 30 and firing multivibrator 69. In this way the desired memory word is read into buffer register 72. At any appropriate time a pulse from the memory control circuits is applied to AND units 10, 11 and gates 12, 14 pass the memory word to stream register 16. When this is done a control pulse is applied to line 80 to switch flip-flop 1, thus raising line 3 to switch momentarily a L/R trigger 18 resulting in an impulse from AND unit 89 which increments the word address by one, and to initiate the action of the local clock. Due to the presence of an inverter circuit 95 the clock will continue running until there is an output from AND units 91 or 87. The contents of the field length register 28 and the bit address register 26 are interpreted by a decoding network activation of one of the AND circuits 63a to 63b to cause a memory access to take place. This occurs when the number of bits in the field length register plus the bit position number gives a bit position in a zone other than that from which data is now being extracted. Trigger 18 conditions either a right-half or lefthalf gate and if the gate is conditioned which gives access to the computed bit position one of AND circuits 60 or 88 is actuated to gate the address in register 30 to memory and thus to transfer the word to buffer 72 and the appropriate half word, when a gating pulse occurs to the stream register. Should it occur that a boundary is to be crossed before the required word is in the zone to be entered one of AND circuits 91 or 87 is actuated and the clock is cut off until the half-word is in the stream register. This is signalled by the switching of trigger 82, when the appropriate AND circuit is de-energized and the clock re-started. A byte extraction cycle includes the following steps : (a) Y pulse from clock. The number of bits to be extracted in the cycle as recorded in register 27 are subtracted by complement addition from the field length in register 28 in a conventional binary adder (Fig. 5, not shown) and the result entered in register 28. The absence of end-around carry, indicating that the field length after the extraction will be negative or zero is used to stop the clock and to reduce the number in the byte register to that which would have produced a zero in the field length register. (b) X pulse. This is gated by a decoding network associated with the bit address register 26 to a control wire in the appropriate bit position of the stream register. Eight bits are always then read out in parallel from the register, but if the bit register 27 records less than eight only a number equal to the setting of the register are gated to use (bit masking: Fig. 4, not shown). (c) Z pulse. The contents of the byte size register are added to the bit address register, as a result of which a memory access may be initiated as described above.

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