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公开(公告)号：EP0205809A2
公开(公告)日：1986-12-30
申请号：EP86105482
申请日：1986-04-21
Applicant: IBM
Inventor： BUCHHOLZ WERNER , SMITH RONALD M , WEHRLY DAVID S
CPC classification number: G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/325 , G06F15/8084
Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.
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公开(公告)号：JPS61290570A
公开(公告)日：1986-12-20
申请号：JP11099086
申请日：1986-05-16
Applicant: IBM
Inventor： BUCHHOLZ WERNER , SMITH RONALD M , WEHRLY DAVID S
Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.
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公开(公告)号：CA630952A
公开(公告)日：1961-11-14
申请号：CA630952D
Applicant: IBM
Inventor： BUCHHOLZ WERNER , CRAWFORD DAVID J , DEUTSCHLE CECIL A
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公开(公告)号：CA651161A
公开(公告)日：1962-10-30
申请号：CA651161D
Applicant: IBM
Inventor： BASHE CHARLES J , CRAGO ROBERT P , FOX PHILIP E , BUCHHOLZ WERNER , PHELPS BYRON E , ROCHESTER NATHANIEL , HADDAD JERRIER A
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公开(公告)号：CA620939A
公开(公告)日：1961-05-30
申请号：CA620939D
Applicant: IBM
Inventor： BUCHHOLZ WERNER , HAYNES MUNRO K , WHITNEY GORDON E
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Patent Agency Ranking
公开(公告)号：DE3685913D1
公开(公告)日：1992-08-13
申请号：DE3685913
申请日：1986-04-21
Applicant: IBM
Inventor： BUCHHOLZ WERNER , SMITH RONALD MORTON , WEHRLY DAVID SILER
Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.
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公开(公告)号：CA1256216A
公开(公告)日：1989-06-20
申请号：CA506750
申请日：1986-04-15
Applicant: IBM
Inventor： BUCHHOLZ WERNER , SMITH RONALD M
Abstract: PO9-55-003 PROGRAM SWITCHING WITH VECTOR REGISTERS The invention relates to vector registers (VRs) which have associated therewith a vector status register (VSR) that includes VR status information in the form of vector in-use and change bits for saving and restoring (the contents of) the VRs. When the vector in-use bit for a VR is zero, the saving and subsequent restoring of the VR is eliminated because the VR is known to contain all zeros. This reduces program switching time. The vector change bit for a VR serves to reduce switching time still further by permitting the saving of a VR to be eliminated when its vector in-use bit is one but the vector change bit is zero. Although such a VR is in use, its content has not been changed since the last restore from the same save area in storage. The previously saved information is still valid. The vector change bits do not affect the restoring of vector registers and, therefore, do not reduce the restore time.
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公开(公告)号：CA1242281A
公开(公告)日：1988-09-20
申请号：CA501738
申请日：1986-02-12
Applicant: IBM
Inventor： BUCHHOLZ WERNER , SMITH RONALD M , WEHRLY DAVID S
Abstract: VECTOR PROCESSING A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number o' elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.
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公开(公告)号：CA631332A
公开(公告)日：1961-11-21
申请号：CA631332D
Applicant: IBM
Inventor： WILD HERBERT K , BUCHHOLZ WERNER , WOLENSKY WILLIAM
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公开(公告)号：DE1111430B
公开(公告)日：1961-07-20
申请号：DEI0009980
申请日：1955-03-21
Applicant: IBM DEUTSCHLAND
Inventor： ROCHESTER NATHANIEL , BASHE CHARLES JULIAN , BUCHHOLZ WERNER , CRAGO ROBERT PAUL , FOX PHILIP EVERETT , HADDAD JERRIER ABDO , PHELPS BYRON EUGENE
IPC: G06F15/78
Abstract: 800,505. Digital electric calculating-apparatus; electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 18, 1955 [March 22, 1954], No. 7918/55. Class 106 (1). Electronic data processing apparatus includes input and output devices interconnected by a computer which employs variable length words, the lengths being demarcated by special coded characters. General. The electronic computer illustrated in Figs. 1a and 1b comprises a C.R.T. memory M, an accumulator including a C.R.T. store AS, and input/output magnetic tape units T. Words comprise a variable number of coded characters each represented by seven bits, Fig. 1c, comprising four numerical bits 1, 2, 4, 8, two zone bits A, B and a redundancy check bit C such as to make the total of " 1 "s in a character always odd. Numbers are in decimal form and have their digits represented in the excess-three code, the zone bits being "0." Words are separated by field marks " +," "-," Fig. 1c, the mark " - " being used only for numbers stored in the memory to indicate a negative sign. In the accumulator store, a negative sign is indicated by numerical " 9 " with " + " field mark zone digits. The field marks and other special characters are detected by recognition circuits CRC associated with two characters registers CR1, CR2, Fig. 1b, which receive characters as they are read out from the memory or accumulator store via main bus MB or accumulator storage bus AB, and also form a buffer between the memory and the tape units. The memory comprises 50 pairs of C.R.T.s; a pair is selected by unit selector US and a " left " or " right " C.R.T. of this pair by memory left/right control MC. The beam in the selected C.R.T. may be deflected to one of 100 character positions by memory deflection circuits MD. The circuits US, MC, MD are controlled by the portions indicated of a 4-decimal-digit address through memory switch MS. A word location is given by the address of the "right-hand " field mark (the one with the higher address number); e.g. the address of the number 123, 456, Fig. 1h, is 0037. Transfer to and from tape (writing and reading) is effected in the order of increasing address numbers (" left to right "), but transfer between the memory and the accumulator is effected in the reverse order (" right to left "). The accumulator store AS, which normally stores one word only, comprises a single C.R.T. having 100 character positions selected by deflection circuits ASD controlled by 2-digit addresses through switch ASS, addresses normally being selected in ascending order. A separate computer cycle is provided for dealing with each character, timing control signals being obtained from clock C and waveform generator WG. An instruction word, e.g. the word at address 0008, Fig. 1h, always comprises 6 characters, viz., an operation-defining character, an " address " portion (4 characters or digits) and a field mark, and is read out from the memory in ascending address order (operation character first). The addresses are sequentially set up in a programme counter PC (in a 1, 2, 2, 4 code) during the 6 successive character cycles of " instruction time," the computer being controlled by instruction timer IT to pass the operation character to interpreter II and the address digits via memory address translator MAT to a register MAR operating in the 1, 2, 2, 4 code. At the commencement of the subsequent " execution time," in which a timer ET is selected to carry out the instruction, the address in register MAR is transferred to counter MAC and normally applied via code ambiguity eliminator MAE to the switch MS to select a required memory location, and the amount registered on a two-decimal-digit starting point counter SPC may be transposed to an accumulator storage address counter AAC and applied via ambiguity eliminator ASAE to switch ASS to select an accumulator location when required. During subsequent execution character cycles, the count in MAC may be stepped down and the count in AAC stepped up to select successive character positions in the memory and accumulator store. Words from M and AS may be sent character by character to the comparator adder time/complement circuits CATC to perform arithmetic and other operations. The flow of information is controlled by routing circuits R. During a portion of each character cycle a regeneration counter RC is effective systematically to regenerate all the stored bits in the C.R.T.s, 50 tubes (one in each pair) being regenerated simultaneously in the main memory M. In some instructions, the memory is not used, and the " address " number in MAC is employed, e.g. to determine how the word stored in AS is to be modified, or to select, through in/out unit selector IOS, one of the tape or other input/ output units. The character emitter CE emits timed pulses representing certain numeral and other characters. The electronic circuits consist primarily of Eccles-Jordan double triode trigger circuits (T), coincidence switches (S) which usually produce a negative output in response to two positive inputs, diode AND and OR circuits, inverters (I) and cathode followers (CF); circuit diagrams for these components are given in the Specification. The computer is described below under the following headings: (1) Clock and waveform generator; timing signal rotation. (2) Basic counter. (3) Ambiguity eliminator. (4) Input/Output. (5) Character Registers and Character Recognition Circuits. (6) Memory address translator and register. (7) Memory address counter and ambiguity eliminator. (8) Programme counter. (9) Regeneration counter. (10) Memory and associated selection circuits. (11) Accumulator storage and associated circuits. (12) Memory and accumulator sign circuits. (13) Comparator, adder, true complement and associated circuits. (14) Adder and complementer. (15) Instruction timer; sequence of events during instruction time. (16) Instruction interpreter. (17) Routing circuits. (18) Execution timers; instructions. (19) Add or subtract instruction. (20) Reset add and subtract instructions. (21) Add to memory instruction. (22) Compare instruction. (23) Multiplication. (24) Division. (25) Instructions involving accumulator, store but not memory, rounding off; positioning decimal point. (26) " Store "-instruction. (27) Transfer of control instructions. (28) Tape instructions. (1) Clock and waveform generator; timing signal notation. The clock C, Fig. 1b, comprises a 1 mc/s. oscillator and a pulse distributing circuit similar to that of Specification 750,259 for defining regeneration (G), and read (R) and write (W) periods in a character cycle. The computer may be held in the " G " portion of the cycle under control of a " repeat regeneration" signal. The clock controls waveform generator circuits WG which develop timing signals such as those shown in Figs. 2c and 2i. Signals are denoted by the number of microseconds their leading edges occur after an index time G0-W7 and by their duration (D); e.g. the pulse L202, Fig. 2i, would be denoted WO1 (D2) meaning a pulse starting 1 Ás. after W0 and lasting 2 Ás. A train of pulses may also be denoted; e.g. R22 (D1)4 indicates 4 pulses each of 1 Ás. duration and starting 2 Ás. after R2 and succeeding index times (L203, Fig. 21). An inverted or complementary signal is indicated by c; e.g. L124c is a positive pulse coinciding with L124, Fig. 2c. (2) Basic counter. A decimal counting circuit CT1, Fig. 1d, comprises four double-triode triggers 101, 102, 103, 104 having weighted values 1, 2 (called 2C), 2, 4 respectively. The triggers may be reset to the " off " or " O " condition (right triode conducting) by a positive pulse at 11, inverted in 131 and applied through diodes 133-136 to the right anodes. Trigger 101 responds to negative input pulses at 15 and, for every second pulse, supplies a negative output pulse to diodes 105 and 107 connected respectively via line 107a to the right-hand input only of trigger 102 and via diode 110 and line 112 to both inputs of 103. Thus, after the second input pulse, trigger 102 is switched " on " and applies a positive gating potential via resistor 108 to diode 107 to allow subsequent pulses from 101 to switch trigger 103. Triggers 101, 103, 104 then operate in normal binary fashion until trigger 104 is switched back to " O " in response to the tenth input pulse, when the negative pulse from its right anode is applied via diode 116 to carry output terminal 27, and to line 118 to reset trigger 102. A value may be entered also in parallel, during a " dumping " operation, by selectively applying "1"-representing negative pulses to terminals 16-19. The registered value may be changed to its 9's complement by a negative pulse applied via 13 to line 126 to switch all the - triggers to the opposite condition, the connections between the triggers being inhibited by applying a positive signal at 12 to inverter 121 so as to drive line 122 negative. Output terminals 21-26 enable the registered value to be read out. After the complementing, and possibly after parallel entry, the representation of any value between 2 and 7 will be different from that obtained during normal stepping of the counter. This alternative representation is translated into the normal one in an ambiguity eliminator (described below). A simplified counter CT2 (Fig. 1e, not shown) having no provision for complementing, also is employed. (3) Ambiguity eliminator. The circuit AE, Fig. 1f, is a code interpreting circuit which receives respectively from terminals 21, 23-26 of a counter such as CT1, Fig. 1d, a negative input at 16 when the " 1 " trigger is " on," positive inputs at 17, 18 when the " 2 " triggers (102 and 103 respectively) are " on," and a positive input at 19 or 20 according to whether the "4" trigger is " off " or " on," and supplies positive outputs selectively to 21-24, corresponding to the weighted values 1, 2G, 2, 4, to represen
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