公开(公告)号：DE2962713D1

公开(公告)日：1982-06-24

申请号：DE2962713

申请日：1979-09-12

Applicant: IBM

Inventor： BROWN DAVID JOHN ,  WALTHER RONALD G ,  WILLIAMS THOMAS WALTER ,  WRIGGLESWORTH MICHAEL DENIS

IPC: G01R31/3185 ,  G06F7/00 ,  G06F11/22 ,  G11C19/00 ,  G11C19/14 ,  G11C19/28 ,  H03K3/027 ,  H03K3/037 ,  H03K3/286 ,  H03K5/15 ,  H03K19/20 ,  H03K23/00 ,  H03K19/003 ,  G11C29/00

Abstract: A shift register latch circuit (FIG. 1) comprised of a polarity hold latch 1 connected to a set/reset latch 2. The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input S to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a 'D' type edge trigger by connecting the clock input +B of the set/reset latch 2 to the clock -C supplied to the polarity hold latch 1. By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.