公开(公告)号：CA2145927A1

公开(公告)日：1995-10-16

申请号：CA2145927

申请日：1995-03-30

Applicant: IBM ,  MOTOROLA INC

Inventor： WRIGHT CHARLES G ,  ALVAREZ JOSE M

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10 ,  H03L7/06 ,  H03L7/197 ,  G06F1/04

Abstract: A method and apparatus are provided for generating a phase-controlled clock signal within a microprocessor. A first clock signal having a first frequency is input. After a reset event, the first clock signal transitions in a first direction at a time t. A second clock signal is output having a second frequency related to the first frequency by a non-integer ratio. The second clock signal transitions in the same direction as the first clock signal at time t.

公开(公告)号：CA1225749A

公开(公告)日：1987-08-18

申请号：CA481595

申请日：1985-05-15

Applicant: IBM

Inventor： WALDECKER DONALD E ,  WRIGHT CHARLES G

IPC: G06F13/36 ,  G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F15/16 ,  G06F13/18

Abstract: AT9-84-011 DATA PROCESSING SYSTEM WITH A PLURALITY OF PROCESSORS ACCESSING A COMMON BUS TO INTERLEAVED STORAGE A plurality of data processor units are connected to a common bus which is connected to first and second interleaved storage units. The system is a synchronous one in which timing means establish a series of information transfer intervals. One or more of the processor units contain apparatus for selectively commencing an address transfer on the bus to one of the storage units during a transfer interval; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors have means for monitoring the bus in order to determine whether an address on the bus has been transferred to the first or the second storage unit during a particular transfer interval. The address transfer apparatus further includes apparatus responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units to thus achieve alternating interleaving between storage units.

公开(公告)号：CA1223967A

公开(公告)日：1987-07-07

申请号：CA485181

申请日：1985-06-25

Applicant: IBM

Inventor： WRIGHT CHARLES G

IPC: G06F13/36

Abstract: INITIALIZATION APPARATUS FOR A DATA PROCESSING SYSTEM WITH A PLURALITY OF INPUT/OUTPUT AND STORAGE CONTROLLER CONNECTED TO A COMMON BUS A plurality of controllers are connected to a common bus in turn connected to a central processor. Each of the controllers respectively serves as an interface between the central processor and at least one storage unit or input/output device. In order for the controllers to distinguish between addresses, the addresses sent from the central processor contain identifier segments indicative of the controller to which the address is being sent. Controllers in turn contain programmable comparison means for comparing the identifier segments in addresses to a stored controller identifier indicative of the controller. Because the comparison means are programmable, controller identifiers have to be set up each time the system is turned on. Consequently, the present invention provides such turn on or initialization means including a read-only initialization program stored in one of the storage units: the controller interfacing with this storage unit becomes a master controller; the master controller has apparatus which is selectively activated only during initialization for accepting all addresses irrespective of the identifier segment. The other controllers have apparatus selectively activated only during initialization for disabling the comparison means and such other controllers so that no addresses are accepted by the other controllers during the initialization. In other words, the comparison means in the master controller is completely bypassed during initialization whereby the read-only initialization program is accessed only through the master controller.

公开(公告)号：BR8800292A

公开(公告)日：1988-09-06

申请号：BR8800292

申请日：1988-01-26

Applicant: IBM

Inventor： HOFFMAN HARRELL ,  WRIGHT CHARLES G

IPC: G06F13/362 ,  G06F13/36