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    Asynchronous interface for use between a main memory and a central processing unit
    1.
    发明授权
    Asynchronous interface for use between a main memory and a central processing unit 失效
    主要存储器与中央处理单元之间使用的异步接口

    公开(公告)号：US3564507A

    公开(公告)日：1971-02-16

    申请号：US3564507D

    申请日：1968-04-10

    Applicant: IBM

    Inventor： FAIVRE RAYMOND W ,  WALDECKER DONALD E

    IPC: G06F13/42 ,  G06F3/04

    CPC classification number: G06F13/4243

    Abstract: AN ASYNCHRONOUS INTERFACE WHICH SELECTIVELY INTERRUPTS THE CLOCK PULSES APPLIED TO A CENTRAL PROCESSING UNIT THEREBY PERMITTING A HIGH SPEED CENTRAL PROCESSING UNIT (CPU) TO OPERATE WITH A LOW SPEED MAIN MEMORY HAVING A RELATIVELY LONG CYCLE TIME OR WITH A PLURALITY OF MAIN MEMORIES HAVING DIFFERENT CYCLE TIMES. THE OPERATION OF THE CPU IS CONTROLLED BY CLOCK PULSES. WHEN THE CPU SELECTS A MAIN MEMORY AND REQUESTS DATA CAN BE PROCESSED, ADDRESS IN THE EMEMORY SO THAT THE DATA CAN BE PROCESSED, A BUSY SIGNAL IS GENERATED FOR A PREDETERMINED FOLLOWING PORTION OF THE SELECTED MEMORY CYCLE. THE BUSY SIGNAL INTERRUPTS THE CLOCK PULSES SO THAT ANOTHER SELECTION OF THE MEMORY CANNOT BE MADE UNTIL THE MEMORY IS READY TO ACCEPT THE ADDRESS OF THE DATA TO BE USED IN THE NEXT REQUEST AT WHICH TIME THE CLOCK PULSES ARE AGAIN APPLIED TO THE CPU. SINCE THE ACCESS TIME OF THE MEMORY MAY BE SO LONG THAT THE REQUESTED DATA IS NOT AVAILABLE AT THE MEMORY OUTPUT WHEN THE CPU IS READY TO ACCEPT AND PROCESS THE DATA, THE CLOCK PULSES ARE INTERRUPTED FOR A PREDETERMINED TIME UNTIL THE DATA IS AVAILABLE, AT WHICH TIME AN ADVANCE SIGNAL IS GENERATED BY THE MEMORY TO INDICATE THE DATA WILL BE AVAILABLE THE NEXT TIME THE CPU IS ABLE TO ACCEPT THIS DATA. BY THE USE OF MEMEORYGENERATED BUSY AND ADVANCE SIGNALS TO INTERRUPT THE CPU CLOCK PUSES, A HIGH SPEED CPU MAY BE USED WITH MEMORIES HAVING DIFFERENT CYCLE TIMES AND DIFFERENT ACCESS TIMES WITHOUT THE NEED FOR CHANGING THE CONTROL LOGIC IN THE CPU.

    Controller for data processing system
    2.
    发明授权
    Controller for data processing system 失效
    数据处理系统控制器

    公开(公告)号：US3396371A

    公开(公告)日：1968-08-06

    申请号：US40001564

    申请日：1964-09-29

    Applicant: IBM

    Inventor： WALDECKER DONALD E

    IPC: G06F9/42 ,  G06F9/46

    CPC classification number: G06F9/4426 ,  G06F9/461

    Abstract: 1,049,984. Computer programming arrangements; delay-line stores. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 24, 1965 [Sept. 29, 1964], No. 36419/65. Headings G4A and G4C. A computer comprises a storage device for storing instructions and data, and a push-down store the contents of a first register of which can be used for securing instructions from storage and can be incremented. Referring to Fig. 5 (not shown), a main store 200 can supply operand and instruction words via a buffer register to an arithmetic unit and field register respectively. Each instruction word has five fields each of which may be an operand address or an operation code as desired except that the first field of a first instruction word must be an operation code. The top three stages of a push-down store 270 are referred to (from the top down) as " instruction counter," " operand counter 1 " and " operand counter 2," and can be used for addressing instructions and operands respectively in the main store, the contents being incremented by one after each use. The first field of the field register is shifted into an operation register and decoded to (a) select (by means of a tag portion) one of the operand counters or the next field(s) of the instruction word as the source of the next operand address(es), (b) set a number from one to four into a field register shift counter to specify the number of field shifts required to place the next operation code in the operation register, (c) control the arithmetic unit, and (d) indicate when a subroutine is to be entered or returned from. For entry to a subroutine, the push-down memory is pushed down one position and the thus-vacated instruction counter is filled with the next field from the instruction word. For exit from a subroutine, the pushdown memory is pushed-up one position so that the contents of operand counter 1 enter the instruction counter &c., and the instruction counter is then used to read out the next instruction word. Thus the return address may be different from the exit address plus one. The number of shifts given to the contents of the field register is counted by a field counter and when it reaches five, the instruction counter is used to obtain another instruction word. Other embodiments.-Simpler similar embodiments having one operation code and one operand address per instruction word, and only one operand counter, and in which the branch address for subroutine entry is passed direct to the main store address register as well as to the push-down memory are described. Delay-line push-down store.-A recirculating delay-line store has provision for advancing or retarding its contents by one time slot on recirculation, and for incrementing the contents of selected slots by one.

    7.
    发明专利
    未知

    公开(公告)号：DE69321929T2

    公开(公告)日：1999-07-01

    申请号：DE69321929

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having intermediate storage buffers (60), general purpose registers (62), and a storage buffer index (58). A particular storage buffer (60) is assigned to a destination operand within a selected multiple scalar instruction. A relationship between the particular intermediate storage buffer (60) and a designated general purpose register (62) is stored in the storage buffer index (58) when the instruction which has been dispatched is replaced in the dispatcher by another instruction. Results of execution from the selected multiple scalar instruction are stored in the particular intermediate storage buffer (60) when the selected instruction is executed. The storage buffer index (58) is used to determine which storage buffers (60) to use as source operands for those instructions which are dispatched between the time that a storage buffer (58) has been assigned for a specific general purpose register (62) and the results of execution are moved from the storage buffer (60) into the general purpose register (62).

    8.
    发明专利
    未知

    公开(公告)号：AT173100T

    公开(公告)日：1998-11-15

    申请号：AT93120933

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having intermediate storage buffers (60), general purpose registers (62), and a storage buffer index (58). A particular storage buffer (60) is assigned to a destination operand within a selected multiple scalar instruction. A relationship between the particular intermediate storage buffer (60) and a designated general purpose register (62) is stored in the storage buffer index (58) when the instruction which has been dispatched is replaced in the dispatcher by another instruction. Results of execution from the selected multiple scalar instruction are stored in the particular intermediate storage buffer (60) when the selected instruction is executed. The storage buffer index (58) is used to determine which storage buffers (60) to use as source operands for those instructions which are dispatched between the time that a storage buffer (58) has been assigned for a specific general purpose register (62) and the results of execution are moved from the storage buffer (60) into the general purpose register (62).

    9.
    发明专利
    未知

    公开(公告)号：DE69322064D1

    公开(公告)日：1998-12-17

    申请号：DE69322064

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

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