公开(公告)号：MX157488A

公开(公告)日：1988-11-25

申请号：MX19547482

申请日：1982-12-07

Applicant: IBM

Inventor： WYAM VIRGIL D ,  KRAFT WAYNE R ,  THOME NANDOR G

IPC: G06F7/00 ,  G06F9/30 ,  G06F13/40 ,  G06F15/78 ,  H01L23/52

Abstract: The signal transfer mechanism includes a plural-bit data bus (16) formed on an integrated circuit chip for transferring plural-bit binary data signals between plural-bit signal source registers (17, 18, 19, 26, 32, 35) and plural-bit signal destination registers (17, 18, 19, 26, 31, 32, 35) formed on the integrated circuit chip, and which are coupled to the plural-bit data bus (16) for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus and a processor control unit (14) enabling one of the signal source register to put a plural-bit data signal onto the data bus (16) during a first processor control cycle and enabling one of the signal destination registers to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.