公开(公告)号：FR2349881A1

公开(公告)日：1977-11-25

申请号：FR7707428

申请日：1977-03-04

Applicant: IBM

Inventor： TUTT WILLIAM E ,  WYATT VIRGIL D

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F12/06 ,  G06F15/16 ,  G06F15/177 ,  G06F9/16 ,  G11C8/00

Abstract: This invention relates to controls for a control store made of plural modules which operate in an overlapped continuous manner, wherein the modules are cycled in a fixed sequence.

公开(公告)号：CA1084633A

公开(公告)日：1980-08-26

申请号：CA281814

申请日：1977-06-30

Applicant: IBM

Inventor： TUTT WILLIAM E ,  WYATT VIRGIL D

IPC: G06F13/00 ,  G06F9/10 ,  G06F9/16 ,  G06F9/20

Abstract: This invention relates generally to control store controls made of plural modules which operate in an overlapped continuous manner, wherein the modules are cycled in a fixed sequence. This invention particularly relates to a novel next address generation and handling means for a control store using time interleaved modules.

公开(公告)号：CA1180456A

公开(公告)日：1985-01-02

申请号：CA417165

申请日：1982-12-07

Applicant: IBM

Inventor： WYATT VIRGIL D ,  KRAFT WAYNE R ,  THOMA NANDOR G

IPC: G06F7/00 ,  G06F9/30 ,  G06F13/40 ,  G06F15/78 ,  H01L23/52

Abstract: LARGE SCALE INTEGRATION DATA PROCESSOR SIGNAL TRANSFER MECHANISM A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus. The signal transfer mechanism further includes processor control circuitry coupled to the signal source and signal destination circuitry for enabling the signal source circuitry to put a plural-bit data signal onto the data bus during a first processor control cycle and for enabling the signal destination circuitry to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.